soc/intel/tigerlake: Move TCSS FW latency macros to tcss.h
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Volteer. Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <soc/iomap.h>
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#include <soc/tcss.h>
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/*
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* Type C Subsystem(TCSS) topology provides Runtime D3 support for USB host controller(xHCI),
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
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* optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
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* port of the USB4/TBT topology.
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*/
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/* Number of microseconds to wait after a conventional reset */
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#define FW_RESET_TIME 50000
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/* Number of microseconds to wait after data link layer active report */
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#define FW_DL_UP_TIME 1
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/* Number of microseconds to wait after a function level reset */
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#define FW_FLR_RESET_TIME 1
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/* Number of microseconds to wait from D3 hot to D0 transition */
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#define FW_D3HOT_TO_D0_TIME 50000
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/* Number of microseconds to wait after setting the VF enable bit */
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#define FW_VF_ENABLE_TIME 1
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OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800)
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Field (PXCS, AnyAcc, NoLock, Preserve)
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{
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#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 0x1088
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#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
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/*
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* The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency
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* optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream
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* port of the USB4/TBT topology.
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*/
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/* Number of microseconds to wait after a conventional reset */
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#define FW_RESET_TIME 50000
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/* Number of microseconds to wait after data link layer active report */
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#define FW_DL_UP_TIME 1
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/* Number of microseconds to wait after a function level reset */
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#define FW_FLR_RESET_TIME 1
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/* Number of microseconds to wait from D3 hot to D0 transition */
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#define FW_D3HOT_TO_D0_TIME 50000
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/* Number of microseconds to wait after setting the VF enable bit */
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#define FW_VF_ENABLE_TIME 1
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#endif /* _SOC_TCSS_H_ */
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