google/panther: Force enable ASPM on PCIe Root Port 4
BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6007 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
parent
c63ad997a5
commit
4923c399f3
|
@ -61,6 +61,9 @@ chip northbridge/intel/haswell
|
||||||
register "sio_i2c0_voltage" = "0" # 3.3V
|
register "sio_i2c0_voltage" = "0" # 3.3V
|
||||||
register "sio_i2c1_voltage" = "0" # 3.3V
|
register "sio_i2c1_voltage" = "0" # 3.3V
|
||||||
|
|
||||||
|
# Force enable ASPM for PCIe Port 4
|
||||||
|
register "pcie_port_force_aspm" = "0x10"
|
||||||
|
|
||||||
# Enable port coalescing
|
# Enable port coalescing
|
||||||
register "pcie_port_coalesce" = "1"
|
register "pcie_port_coalesce" = "1"
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue