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mb/intel/mtlrvp: Configure USB devices for MTL-RVP 

This patch adds OC configuration of USB devices for MTL-RVP
as per MTL-RVP design specification,

USB 2.0
usb2_ports0 -> OC0
usb2_ports1 -> OC0
usb2_ports2 -> OC0
usb2_ports3 -> OC0
usb2_ports4 -> OC0
usb2_ports5 -> OC0
usb2_ports6 -> OC_SKIP
usb2_ports7 -> OC_SKIP
usb2_ports8 -> OC_SKIP
usb2_ports9 -> OC_SKIP

USB 3.2 Gen 2x1
usb3_ports0 -> OC0
usb3_ports1 -> OC0

TCPx
tcss_ports0 -> OC0
tcss_ports1 -> OC0
tcss_ports2 -> OC0
tcss_ports3 -> OC0

BUG=b:224325352
TEST=Able to build with the patch and boot the mtlrvp to chromeOS
(on top of CB: 66190).

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: If1a0c31b7bf0f3fc06f039ad76b0cdd41f7cdd90
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This commit is contained in:
Harsha B R 2022-12-21 11:08:46 +05:30 committed by Sridhar Siricilla
parent 8b32e404e1
commit 4954a0f611
1 changed files with 19 additions and 0 deletions
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19
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -17,6 +17,25 @@ chip soc/intel/meteorlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled,
}" }"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0
register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN / MCF
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # MCF / M.2 WWAN
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A1 / M.2 WWAN
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A0 / USB Flex Connector
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)"
device domain 0 on device domain 0 on
device ref igpu on end device ref igpu on end
device ref heci1 on end device ref heci1 on end