mb/google/brya/var/taeko: Correct comments to prevent confusion

The PCIE RP 9 on taeko is for eMMC.
Correct the comments to prevent confusion.

BUG=b:271003060

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib49942b682d1817af9e8b4b61044aa170e18fea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/mainboard/google/brya/variants/taeko/overridetree.cb

@@ -532,7 +532,7 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie_rp9 on
-			# Enable NVMe PCIE 9 using clk 0
+			# Enable PCIE 9 using clk 0 for eMMC
 			register "pch_pcie_rp[PCH_RP(9)]" = "{
 				.clk_src = 0,
 				.clk_req = 0,