soc/rockchip/rk3399: Convert to `board_reset()`
Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -47,7 +47,6 @@ config BOARD_SPECIFIC_OPTIONS
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_RTC
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select EC_GOOGLE_CHROMEEC_SPI
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select HAVE_HARD_RESET
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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@ -18,7 +18,7 @@
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#include "board.h"
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void do_hard_reset(void)
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void do_board_reset(void)
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{
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gpio_output(GPIO_RESET, 1);
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}
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@ -990,7 +990,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR,
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"index1 frequency change overtime, reset\n");
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hard_reset();
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board_reset();
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}
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}
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@ -1000,7 +1000,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
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if (stopwatch_expired(&sw)) {
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printk(BIOS_ERR,
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"index1 frequency done overtime, reset\n");
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hard_reset();
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board_reset();
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}
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}
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@ -1009,7 +1009,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
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clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
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if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
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printk(BIOS_ERR, "index1 training failed, reset\n");
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hard_reset();
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board_reset();
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}
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}
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}
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@ -1042,7 +1042,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
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*/
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if (pctl_cfg(channel, sdram_params) != 0) {
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printk(BIOS_ERR, "pctl_cfg fail, reset\n");
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hard_reset();
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board_reset();
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}
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/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
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@ -1052,7 +1052,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
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if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
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printk(BIOS_ERR,
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"SDRAM initialization failed, reset\n");
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hard_reset();
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board_reset();
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}
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set_ddrconfig(sdram_params, channel,
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