reset: Convert individual boards to `board_reset()`

Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

src/mainboard/google/foster/pmic.c

@@ -44,7 +44,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int delay)
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
 			__func__, reg, val);
 		/* Reset the board on any PMIC write error */
-		hard_reset();
+		board_reset();
 	} else {
 		if (delay)
 			udelay(500);

src/mainboard/google/foster/reset.c

@@ -18,7 +18,7 @@
 #include <gpio.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	gpio_output(GPIO(I5), 0);
 }

src/mainboard/google/gale/Kconfig

@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_8192
 	select COMMON_CBFS_SPI_WRAPPER
 	select DRIVERS_I2C_WW_RING
-	select HAVE_HARD_RESET
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH
 	select SPI_FLASH_GIGADEVICE

src/mainboard/google/gale/reset.c

@@ -19,7 +19,7 @@
 #include <soc/iomap.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	/*
 	 * At boot time the boot loaders would have set a magic cookie

src/mainboard/google/nyan/pmic.c

@@ -61,7 +61,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
 			__func__, reg, val);
 		/* Reset the SoC on any PMIC write error */
-		hard_reset();
+		board_reset();
 	} else {
 		if (do_delay)
 			udelay(500);

src/mainboard/google/nyan/reset.c

@@ -13,11 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
         gpio_output(GPIO(I5), 0);
 }

src/mainboard/google/nyan/romstage.c

@@ -76,7 +76,7 @@ static void __attribute__((noinline)) romstage(void)
 	 */
 	if (power_reset_status() == POWER_RESET_WATCHDOG) {
 		printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
-		hard_reset();
+		board_reset();
 	}
 
 	/* FIXME: this may require coordination with moving timestamps */

src/mainboard/google/nyan_big/pmic.c

@@ -61,7 +61,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
 			__func__, reg, val);
 		/* Reset the SoC on any PMIC write error */
-		hard_reset();
+		board_reset();
 	} else {
 		if (do_delay)
 			udelay(500);

src/mainboard/google/nyan_big/reset.c

@@ -13,11 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
         gpio_output(GPIO(I5), 0);
 }

src/mainboard/google/nyan_big/romstage.c

@@ -76,7 +76,7 @@ static void __attribute__((noinline)) romstage(void)
 	 */
 	if (power_reset_status() == POWER_RESET_WATCHDOG) {
 		printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
-		hard_reset();
+		board_reset();
 	}
 
 	/* FIXME: this may require coordination with moving timestamps */

src/mainboard/google/nyan_blaze/pmic.c

@@ -61,7 +61,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
 			__func__, reg, val);
 		/* Reset the SoC on any PMIC write error */
-		hard_reset();
+		board_reset();
 	} else {
 		if (do_delay)
 			udelay(500);

src/mainboard/google/nyan_blaze/reset.c

@@ -13,11 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
         gpio_output(GPIO(I5), 0);
 }

src/mainboard/google/nyan_blaze/romstage.c

@@ -80,7 +80,7 @@ static void __attribute__((noinline)) romstage(void)
 	 */
 	if (power_reset_status() == POWER_RESET_WATCHDOG) {
 		printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
-		hard_reset();
+		board_reset();
 	}
 
 	/* FIXME: this may require coordination with moving timestamps */

src/mainboard/google/purin/Kconfig

@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ROMSIZE_KB_2048
 	select COMMON_CBFS_SPI_WRAPPER
-	select HAVE_HARD_RESET
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_BROADCOM_CYGNUS
 	select SPI_FLASH

src/mainboard/google/purin/reset.c

@@ -15,6 +15,6 @@
 
 #include <reset.h>
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 }

src/mainboard/google/smaug/pmic.c

@@ -47,7 +47,7 @@ static void pmic_write_reg(unsigned bus, uint8_t chip, uint8_t reg, uint8_t val,
 		printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
 			__func__, reg, val);
 		/* Reset the board on any PMIC write error */
-		hard_reset();
+		board_reset();
 	} else {
 		if (delay)
 			udelay(500);

src/mainboard/google/smaug/reset.c

@@ -18,7 +18,7 @@
 
 #include "gpio.h"
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	gpio_output(AP_SYS_RESET_L, 0);
 }

src/mainboard/google/storm/Kconfig

@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_8192
 	select COMMON_CBFS_SPI_WRAPPER
 	select DRIVERS_I2C_WW_RING
-	select HAVE_HARD_RESET
 	select MAINBOARD_HAS_CHROMEOS
 	select SPI_FLASH
 	select SPI_FLASH_SPANSION

src/mainboard/google/storm/reset.c

@@ -39,7 +39,7 @@ static void wdog_reset(void)
 	write32(APCS_WDT0_CPU0_WDOG_EXPIRED_ENABLE, 1);
 }
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	wdog_reset();
 }

src/mainboard/google/veyron/Kconfig

@@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOC_ROCKCHIP_RK3288
 	select MAINBOARD_HAS_CHROMEOS
 	select BOARD_ROMSIZE_KB_4096
-	select HAVE_HARD_RESET
 	select SPI_FLASH
 	select SPI_FLASH_GIGADEVICE
 	select SPI_FLASH_WINBOND

src/mainboard/google/veyron/reset.c

@@ -13,13 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
 #include "board.h"
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
 }

src/mainboard/google/veyron_mickey/Kconfig

@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ROMSIZE_KB_4096
 	select COMMON_CBFS_SPI_WRAPPER
-	select HAVE_HARD_RESET
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_ROCKCHIP_RK3288
 	select SPI_FLASH

src/mainboard/google/veyron_mickey/reset.c

@@ -13,13 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
 #include "board.h"
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
 }

src/mainboard/google/veyron_rialto/Kconfig

@@ -19,7 +19,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select BOARD_ROMSIZE_KB_4096
 	select COMMON_CBFS_SPI_WRAPPER
-	select HAVE_HARD_RESET
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_ROCKCHIP_RK3288
 	select SPI_FLASH

src/mainboard/google/veyron_rialto/reset.c

@@ -13,13 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <gpio.h>
 #include <reset.h>
 
 #include "board.h"
 
-void do_hard_reset(void)
+void do_board_reset(void)
 {
 	gpio_output(GPIO_RESET, 1);
 }

src/soc/nvidia/tegra124/Kconfig

@@ -7,7 +7,6 @@ config SOC_NVIDIA_TEGRA124
 	select ARCH_ROMSTAGE_ARMV7
 	select ARCH_RAMSTAGE_ARMV7
 	select HAVE_UART_SPECIAL
-	select HAVE_HARD_RESET
 	select HAVE_MONOTONIC_TIMER
 	select GENERIC_UDELAY
 	select BOOTBLOCK_CONSOLE

src/soc/nvidia/tegra210/Kconfig

@@ -10,7 +10,6 @@ config SOC_NVIDIA_TEGRA210
 	select GIC
 	select HAVE_MONOTONIC_TIMER
 	select GENERIC_UDELAY
-	select HAVE_HARD_RESET
 	select HAVE_UART_SPECIAL
 	select ARM64_USE_ARM_TRUSTED_FIRMWARE
 	select GENERIC_GPIO_LIB