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soc/rockchip/rk3399: Convert to `board_reset()` 

Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Nico Huber 2018-10-06 17:56:17 +02:00 committed by Patrick Georgi
parent e8791361b5
commit 496fb23c5d
3 changed files with 6 additions and 7 deletions
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1
src/mainboard/google/gru/Kconfig
View File

@ -47,7 +47,6 @@ config BOARD_SPECIFIC_OPTIONS
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_RTC select EC_GOOGLE_CHROMEEC_RTC
select EC_GOOGLE_CHROMEEC_SPI select EC_GOOGLE_CHROMEEC_SPI
select HAVE_HARD_RESET
select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT

2
src/mainboard/google/gru/reset.c
View File

@ -18,7 +18,7 @@
#include "board.h" #include "board.h"
void do_hard_reset(void) void do_board_reset(void)
{ {
gpio_output(GPIO_RESET, 1); gpio_output(GPIO_RESET, 1);
} }

10
src/soc/rockchip/rk3399/sdram.c
View File

@ -990,7 +990,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
if (stopwatch_expired(&sw)) { if (stopwatch_expired(&sw)) {
printk(BIOS_ERR, printk(BIOS_ERR,
"index1 frequency change overtime, reset\n"); "index1 frequency change overtime, reset\n");
hard_reset(); board_reset();
} }
} }
@ -1000,7 +1000,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
if (stopwatch_expired(&sw)) { if (stopwatch_expired(&sw)) {
printk(BIOS_ERR, printk(BIOS_ERR,
"index1 frequency done overtime, reset\n"); "index1 frequency done overtime, reset\n");
hard_reset(); board_reset();
} }
} }
@ -1009,7 +1009,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
printk(BIOS_ERR, "index1 training failed, reset\n"); printk(BIOS_ERR, "index1 training failed, reset\n");
hard_reset(); board_reset();
} }
} }
} }
@ -1042,7 +1042,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
*/ */
if (pctl_cfg(channel, sdram_params) != 0) { if (pctl_cfg(channel, sdram_params) != 0) {
printk(BIOS_ERR, "pctl_cfg fail, reset\n"); printk(BIOS_ERR, "pctl_cfg fail, reset\n");
hard_reset(); board_reset();
} }
/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
@ -1052,7 +1052,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
if (data_training(channel, sdram_params, PI_FULL_TRAINING)) { if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
printk(BIOS_ERR, printk(BIOS_ERR,
"SDRAM initialization failed, reset\n"); "SDRAM initialization failed, reset\n");
hard_reset(); board_reset();
} }
set_ddrconfig(sdram_params, channel, set_ddrconfig(sdram_params, channel,