tegra132: Make non-vboot2 memlayout more useful

Update non-vboot2 memlayout:
1) Add timestamp region
2) Increase ramstage size
3) Change name from memlayout_vboot.ld to memlayout.ld so that any non-vboot
upstream board can also use this layout.

BUG=None
BRANCH=None
TEST=Compiles and boots to kernel prompt on ryu with vboot selected instead of
vboot2.

Change-Id: Idced98f9df7cdbab5f62cd1e382c6046ade1d867
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20fffa282b20fb32ce2ff687f4479be630f90fcf
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I91accd54efc53ab563a2063b9c6e9390f5dd527f
Original-Reviewed-on: https://chromium-review.googlesource.com/231547
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9536
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh 2014-11-21 17:07:16 -08:00 committed by Patrick Georgi
parent d56abd7d7a
commit 49aa78adba
3 changed files with 7 additions and 6 deletions

View File

@ -1,5 +1,5 @@
#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
#include <soc/memlayout_vboot2.ld> #include <soc/memlayout_vboot2.ld>
#else #else
#include <soc/memlayout_vboot.ld> #include <soc/memlayout.ld>
#endif #endif

View File

@ -1,5 +1,5 @@
#if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE) #if IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)
#include <soc/memlayout_vboot2.ld> #include <soc/memlayout_vboot2.ld>
#else #else
#include <soc/memlayout_vboot.ld> #include <soc/memlayout.ld>
#endif #endif

View File

@ -32,12 +32,13 @@ SECTIONS
{ {
SRAM_START(0x40000000) SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K) PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
CBFS_CACHE(0x40002000, 88K) PRERAM_CBFS_CACHE(0x40002000, 84K)
STACK(0x40018000, 16K) STACK(0x40017000, 16K)
BOOTBLOCK(0x4001C000, 20K) BOOTBLOCK(0x4001B800, 22K)
ROMSTAGE(0x40021000, 124K) ROMSTAGE(0x40021000, 124K)
SRAM_END(0x40040000) SRAM_END(0x40040000)
DRAM_START(0x80000000) DRAM_START(0x80000000)
RAMSTAGE(0x80200000, 192K) POSTRAM_CBFS_CACHE(0x80100000, 1M)
RAMSTAGE(0x80200000, 256K)
} }