arch/x86: Remove XIP_ROM_SIZE
When adding XIP stages on x86, the -P parameter was used to pass a page size that covers the entire file to add. The same can now be achieved with --pow2page and we no longer need to define a static Konfig for the purpose. TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and inspect the generated make.log files. The effective pagesize is reduced from 64kB to 16kB for asus/p2b giving more freedom for the stage placement inside CBFS. Pagesize remained at 64kB for lenovo/x60. Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Hui <buurin@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -1177,10 +1177,8 @@ $(CONFIG_CBFS_PREFIX)/romstage-options := -S ".car.data"
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ifneq ($(CONFIG_NO_XIP_EARLY_STAGES),y)
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$(CONFIG_CBFS_PREFIX)/romstage-options += --xip
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# If XIP_ROM_SIZE isn't being used don't overly constrain romstage by passing
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# -P with a default value.
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ifneq ($(CONFIG_NO_FIXED_XIP_ROM_SIZE),y)
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$(CONFIG_CBFS_PREFIX)/romstage-options += -P $(CONFIG_XIP_ROM_SIZE)
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$(CONFIG_CBFS_PREFIX)/romstage-options += --pow2page
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endif # CONFIG_NO_FIXED_XIP_ROM_SIZE
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endif # CONFIG_NO_XIP_EARLY_STAGES
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@ -70,11 +70,6 @@ config NO_FIXED_XIP_ROM_SIZE
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to unnecessary alignment constraints in cbfs for romstage.
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Therefore, allow those chipsets a path to not be burdened.
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config XIP_ROM_SIZE
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hex
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depends on !NO_FIXED_XIP_ROM_SIZE
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default 0x10000
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config SETUP_XIP_CACHE
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bool
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depends on !NO_XIP_EARLY_STAGES
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@ -190,10 +190,6 @@ static inline unsigned int fls(unsigned int x)
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*/
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#define CACHE_TMP_RAMTOP (16<<20)
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#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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/* For ROM caching, generally, try to use the next power of 2. */
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#define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
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#define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE)
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