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soc/intel/alderlake: Add PMC register base for ADL-N 

Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated
from the FSP code.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Usha P 2022-01-17 19:04:32 +05:30 committed by Subrata Banik
parent 01e426d217
commit 4b4aa0bed6
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/alderlake/bootblock/pch.c
View File

@ -25,7 +25,12 @@
#include <soc/pcr_ids.h> #include <soc/pcr_ids.h>
#include <soc/pm.h> #include <soc/pm.h>
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1080
#else
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100
#endif
#define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR0 0
#define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR1 0x4
#define PCR_PSFX_TO_SHDW_BAR2 0x8 #define PCR_PSFX_TO_SHDW_BAR2 0x8