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sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

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For all these southbridges, the lower nibble of PCICMD is read-only.

Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.

Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-10-30 17:36:16 +01:00
parent 344a1bd43c
commit 4b519f7c62
7 changed files with 0 additions and 35 deletions
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5
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -519,11 +519,6 @@ static void lpc_init(struct device *dev)
/* Print detected platform */
report_pch_info(dev);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);

5
src/southbridge/intel/i82801dx/lpc.c
View file

@ -252,11 +252,6 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
i82801dx_enable_acpi(dev);
/* IO APIC initialization. */
i82801dx_enable_ioapic(dev);

5
src/southbridge/intel/i82801gx/lpc.c
View file

@ -341,11 +341,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801gx_enable_ioapic(dev);

5
src/southbridge/intel/i82801ix/lpc.c
View file

@ -355,11 +355,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801ix_enable_apic(dev);

5
src/southbridge/intel/i82801jx/lpc.c
View file

@ -347,11 +347,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
i82801jx_enable_apic(dev);

5
src/southbridge/intel/ibexpeak/lpc.c
View file

@ -433,11 +433,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);

5
src/southbridge/intel/lynxpoint/lpc.c
View file

@ -505,11 +505,6 @@ static void lpc_init(struct device *dev)
{
printk(BIOS_DEBUG, "pch: %s\n", __func__);
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* IO APIC initialization. */
pch_enable_ioapic(dev);