mb/google/dragonegg: Pass FSP-M UPD as per dragonegg requirement
TEST=Able to boot dragonegg board with LPDDR4 memory. Change-Id: Idbe0aa79879f2b1a754dd1f6718ad4ba1173e760 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31956 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,9 +13,74 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <assert.h>
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <cbfs.h>
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#include <console/console.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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static uintptr_t mainboard_get_spd_data(void)
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{
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char *spd_file;
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size_t spd_file_len;
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int spd_index;
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const size_t spd_len = CONFIG_DIMM_SPD_SIZE;
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const char *spd_bin = "spd.bin";
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spd_index = variant_memory_sku();
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assert(spd_index >= 0);
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printk(BIOS_INFO, "SPD index %d\n", spd_index);
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/* Load SPD data from CBFS */
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spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD,
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&spd_file_len);
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if (!spd_file)
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die("SPD data not found.");
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/* make sure we have at least one SPD in the file. */
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if (spd_file_len < spd_len)
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die("Missing SPD data.");
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/* Make sure we did not overrun the buffer */
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if (spd_file_len < ((spd_index + 1) * spd_len))
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die("Invalid SPD index.");
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spd_index *= spd_len;
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return (uintptr_t)(spd_file + spd_index);
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}
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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{
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FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
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struct lpddr4_config mem_params;
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memset(&mem_params, 0, sizeof(mem_params));
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variant_memory_params(&mem_params);
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if (mem_params.dq_map && mem_params.dq_map_size)
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memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map,
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mem_params.dq_map_size);
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if (mem_params.dqs_map && mem_params.dqs_map_size)
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memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map,
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mem_params.dqs_map_size);
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memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor,
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mem_params.rcomp_resistor_size);
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memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target,
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mem_params.rcomp_target_size);
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mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
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mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
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mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
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mem_cfg->DqPinsInterleaved = 0;
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mem_cfg->CaVrefConfig = 0x2;
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mem_cfg->ECT = 1; /* Early Command Training Enabled */
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mem_cfg->RefClk = 0; /* Auto Select CLK freq */
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mem_cfg->SpdAddressTable[0] = 0x0;
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mem_cfg->SpdAddressTable[1] = 0x0;
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mem_cfg->SpdAddressTable[2] = 0x0;
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mem_cfg->SpdAddressTable[3] = 0x0;
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}
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}
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@ -102,8 +102,8 @@ chip soc/intel/icelake
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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}"
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}"
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register "SerialIoGSpiMode" = "{
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register "SerialIoGSpiMode" = "{
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