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mb/ocp/wedge100s: Add SuperIO support 

* Enable COM1, COM2, PMC1 and PMC2

TODO: Look at additional configuration and EC space.

Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.

Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2019-01-16 14:51:18 +01:00 committed by Felix Held
parent 5449007425
commit 4c2ce72341
2 changed files with 34 additions and 1 deletions
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2
src/mainboard/ocp/wedge100s/Kconfig
View File

@ -9,13 +9,13 @@ config BOARD_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
select SERIRQ_CONTINUOUS_MODE
select SUPERIO_ITE_COMMON_PRE_RAM
select FSP_EHCI1_ENABLE
select MRC_CACHE_FMAP
select ENABLE_FSP_FAST_BOOT
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM1
select DRIVERS_UART_8250IO
select SUPERIO_ITE_IT8528E
config VBOOT
select VBOOT_VBNV_CMOS

33
src/mainboard/ocp/wedge100s/devicetree.cb
View File

@ -11,6 +11,39 @@ chip soc/intel/fsp_broadwell_de
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip superio/ite/it8528e
# COM1, routed to COM-e header
device pnp 6e.1 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
# COM2, routed to COM-e header
device pnp 6e.2 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 6e.4 off end
device pnp 6e.5 off end
device pnp 6e.6 off end
device pnp 6e.a off end
device pnp 6e.f off end
device pnp 6e.10 off end
device pnp 6e.11 on
io 0x60 = 0x62
io 0x62 = 0x66
irq 0x70 = 1
end
device pnp 6e.12 on
io 0x60 = 0x68
io 0x62 = 0x6c
irq 0x70 = 1
end
device pnp 6e.13 off end
device pnp 6e.14 off end
device pnp 6e.17 off end
device pnp 6e.18 off end
device pnp 6e.19 off end
end #superio/ite/it8528e
end # LPC Bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus Controller