cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth
Stefan Reinauer
parent
0cb07e3476
commit
4c3ab7376e
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@ -88,7 +88,7 @@ static void post_cache_as_ram(void)
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#endif
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#if 1
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{
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/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
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/* Check value of esp to verify if we have enough room for stack in Cache as RAM */
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unsigned v_esp;
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__asm__ volatile (
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"movl %%esp, %0\n\t"
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@ -123,7 +123,7 @@ static void post_cache_as_ram(void)
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/* set new esp */ /* before CONFIG_RAMBASE */
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"subl %0, %%esp\n\t"
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::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
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/* discard all registers (eax is used for %0), so gcc redo everything
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/* discard all registers (eax is used for %0), so gcc redoes everything
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after the stack is moved */
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: "cc", "memory", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp"
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);
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@ -91,10 +91,10 @@ unsigned get_apicid_base(unsigned ioapic_num)
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}
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#endif
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//contruct apicid_base
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//Construct apicid_base
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if((!disable_siblings) && (siblings>0) ) {
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/* for 8 way dual core, we will used up apicid 16:16, actualy 16 is not allowed by current kernel
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/* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel
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and the kernel will try to get one that is small than 16 to make io apic work.
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I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */
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@ -163,7 +163,7 @@ static void eng2900(void)
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* clocks when CPU is snooped. Because setting XSTATE to 0
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* overrides any other XSTATE action, the code will always
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* stall for 4 GeodeLink clocks after a snoop request goes
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* away even if it occured a clock or two later than a
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* away even if it occurred a clock or two later than a
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* different snoop; the stall signal will never 'glitch high'
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* for only one or two CPU clocks with this code.
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*/
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@ -201,7 +201,7 @@ static void eng2900(void)
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msr.lo = 0x30000;
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wrmsr(MSR_GLCP + 0x0073, msr);
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/* Writing action number 5: STALL_CPU_PIPE when exitting idle
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/* Writing action number 5: STALL_CPU_PIPE when exiting idle
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state or not in idle state */
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msr.hi = 0;
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msr.lo = 0x00430000;
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@ -293,7 +293,7 @@ static void bug118339(void)
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*
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* PBZ 3659:
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* The MC reordered transactions incorrectly and breaks coherency.
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* Disable reording and take a potential performance hit.
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* Disable reordering and take a potential performance hit.
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* This is safe to do here and not in MC init since there is nothing
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* to maintain coherency with and the cache is not enabled yet.
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*/
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@ -119,7 +119,7 @@ void cpuRegInit (void)
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wrmsr(msrnum, msr);
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}
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/* FPU impercise exceptions bit */
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/* FPU imprecise exceptions bit */
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{
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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@ -67,7 +67,7 @@ static void pcideadlock(void)
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/***/
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/** PBZ 3659:*/
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/** The MC reordered transactions incorrectly and breaks coherency.*/
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/** Disable reording and take a potential performance hit.*/
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/** Disable reordering and take a potential performance hit.*/
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/** This is safe to do here and not in MC init since there is nothing*/
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/** to maintain coherency with and the cache is not enabled yet.*/
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/***/
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@ -54,7 +54,7 @@ static const struct {
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{ DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
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0x00000000, 0x00000000,
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0x00000000, 0x00000C00 }, /* Errata 326 */
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0x00000000, 0x00000C00 }, /* Erratum 326 */
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{ NB_CFG, AMD_FAM10_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
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0x00000000, 1 << 22,
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@ -68,7 +68,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
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9.- TODO Requires information on current delivery capability
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(depends on mainboard and maybe power supply ?). One might use a config
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option with the maximum number of Ampers that the board can deliver to CPU.
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option with the maximum number of Amperes that the board can deliver to CPU.
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10.- [Multiprocessor] TODO 2.4.2.12
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[Uniprocessor] FIXME ? We call setPStateMaxVal() in init_fidvid_stage2,
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@ -79,7 +79,7 @@ Fam10 Bios and Kernel Development Guide #31116, rev 3.48, April 22, 2010
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11.- finalPstateChange() from init_fidvid_Stage2 (BKDG says just "may", anyway)
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12.- generate ACPI for p-states. FIXME
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Needs more assesment. There's some kind of fixed support that
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Needs more assessment. There's some kind of fixed support that
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does not seem to depend on CPU revision or actual MSRC001_00[68:64]
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as BKDG apparently requires.
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http://www.coreboot.org/ACPI#CPU_Power_Management
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@ -935,7 +935,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
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static void finalPstateChange(void)
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{
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/* Enble P0 on all cores for best performance.
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/* Enable P0 on all cores for best performance.
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* Linux can slow them down later if need be.
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* It is safe since they will be in C1 halt
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* most of the time anyway.
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@ -424,7 +424,7 @@ static void start_node(u8 node)
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/**
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* static void setup_remote_node(u32 node)
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*
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* Copy the BSP Adress Map to each AP.
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* Copy the BSP Address Map to each AP.
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*/
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static void setup_remote_node(u8 node)
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{
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@ -496,7 +496,7 @@ static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
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continue;
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if ((readback & 0xff) == 2) {
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timeout = 0;
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break; /* target ap is stage 2, it's FID has beed set */
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break; /* target ap is stage 2, its FID has been set */
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}
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}
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@ -603,7 +603,7 @@ static void init_fidvid_bsp(unsigned bsp_apicid)
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/* For all APs ( We know the APIC ID of all AP even the APIC ID is lifted)
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* send signal to the AP it could change it's fid/vid */
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/* remote read singnal from AP that AP is done */
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/* remote read signal from AP that AP is done */
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fv.common_fidvid &= 0xffff00;
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@ -509,7 +509,7 @@ static void model_fxx_init(device_t dev)
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id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
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/* Is this a bad location? In particular can another node prefecth
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/* Is this a bad location? In particular can another node prefetch
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* data from this node before we have initialized it?
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*/
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if (id.coreid == 0)
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@ -75,7 +75,7 @@ static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid
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#if CONFIG_K8_REV_F_SUPPORT
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/*
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* Details about this algorithm , refert to BDKG 10.5.1
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* Details about this algorithm , refer to BDKG 10.5.1
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* Two parts are included, the another is the DSDT reconstruction process
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*/
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@ -202,7 +202,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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goto write_pstates;
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}
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/* Get the multipier of the fid frequency */
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/* Get the multiplier of the fid frequency */
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/*
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* Fid multiplier is always 100 revF and revG.
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*/
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@ -316,7 +316,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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Pstate_num++;
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}
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/* Constuct P[Min] State */
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/* Construct P[Min] State */
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if (Max_fid == 0x2A && Max_vid != 0x0) {
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Pstate_fid[Pstate_num] = 0x2;
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Pstate_feq[Pstate_num] =
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@ -131,7 +131,7 @@ void amd_setup_mtrrs(void)
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* Set up the mtrrs so we can cache the memory.
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*/
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// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
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// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
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// variable MTRR to span memory above 4GB
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// Lower revisions K8 need variable MTRR over 4GB
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x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
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@ -95,10 +95,10 @@ u32 get_apicid_base(u32 ioapic_num)
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nb_cfg_54 = read_nb_cfg_54();
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//contruct apicid_base
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//Construct apicid_base
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if((!disable_siblings) && (siblings>0) ) {
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/* for 8 way dual core, we will used up apicid 16:16, actualy
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/* for 8 way dual core, we will used up apicid 16:16, actually
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16 is not allowed by current kernel and the kernel will try
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to get one that is small than 16 to make io apic work. I don't
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know when the kernel can support 256 apic id.
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@ -169,7 +169,7 @@ void smm_initiate_relocation(void);
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void smm_initiate_relocation_parallel(void);
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struct bus;
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void bsp_init_and_start_aps(struct bus *cpu_bus);
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/* Returns 0 on succes. < 0 on failure. */
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/* Returns 0 on success. < 0 on failure. */
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int setup_ap_init(struct bus *cpu_bus, int *max_cpus,
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const void *microcode_patch);
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/* Returns 0 on success, < 0 on failure. */
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@ -39,7 +39,7 @@
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#include "chip.h"
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/*
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* List of suported C-states in this processor
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* List of supported C-states in this processor
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*
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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@ -324,7 +324,7 @@ static void configure_thermal_target(void)
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return;
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conf = lapic->chip_info;
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/* Set TCC activaiton offset if supported */
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/* Set TCC activation offset if supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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@ -508,8 +508,8 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
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int num_aps;
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const void *microcode_patch;
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/* Perform any necesarry BSP initialization before APs are brought up.
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* This call alos allows the BSP to prepare for any secondary effects
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/* Perform any necessary BSP initialization before APs are brought up.
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* This call also allows the BSP to prepare for any secondary effects
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* from calling cpu_initialize() such as smm_init(). */
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bsp_init_before_ap_bringup(cpu_bus);
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@ -529,7 +529,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus)
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}
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if (smm_initialize()) {
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printk(BIOS_CRIT, "SMM Initialiazation failed...\n");
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printk(BIOS_CRIT, "SMM Initialization failed...\n");
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return;
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}
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@ -78,7 +78,7 @@ static device_t cpu_devs[CONFIG_MAX_CPUS];
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static atomic_t num_aps;
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/* Number of APs that have relocated their SMM handler. */
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static atomic_t num_aps_relocated_smm;
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/* Barrier to stop APs from performing SMM relcoation. */
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/* Barrier to stop APs from performing SMM relocation. */
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static int smm_relocation_barrier_begin __attribute__ ((aligned (64)));
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/* Determine if hyperthreading is disabled. */
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int ht_disabled;
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@ -145,7 +145,7 @@ void release_aps_for_smm_relocation(int do_parallel)
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/* The mtrr code sets up ROM caching on the BSP, but not the others. However,
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* the boot loader payload disables this. In order for Linux not to complain
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* ensure the caching is disabled for tha APs before going to sleep. */
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* ensure the caching is disabled for the APs before going to sleep. */
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static void cleanup_rom_caching(void)
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{
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x86_mtrr_disable_rom_caching();
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@ -178,7 +178,7 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr)
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ap_initiate_smm_relocation();
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/* Indicate that SMM relocation has occured on this thread. */
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/* Indicate that SMM relocation has occurred on this thread. */
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atomic_inc(&num_aps_relocated_smm);
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/* After SMM relocation a 2nd microcode load is required. */
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@ -401,7 +401,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, int *total_hw_threads)
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/* Allocate the new cpu device structure */
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new = alloc_find_dev(cpu_bus, &cpu_path);
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if (new == NULL) {
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printk(BIOS_CRIT, "Could not allocte cpu device\n");
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printk(BIOS_CRIT, "Could not allocate cpu device\n");
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max_cpus--;
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}
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cpu_devs[i] = new;
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@ -348,7 +348,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
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memset(ied_base + (1 << 20), 0, (32 << 10));
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/* According to the BWG MP init section 2MiB of memory at IEDBASE +
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* 2MiB should be zeroed as well. However, I suspect what is inteneded
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* 2MiB should be zeroed as well. However, I suspect what is intended
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* is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
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//memset(ied_base + (2 << 20), 0, (2 << 20));
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}
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@ -39,7 +39,7 @@
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#include "chip.h"
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/*
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* List of suported C-states in this processor
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* List of supported C-states in this processor
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*
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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@ -249,7 +249,7 @@ static void configure_thermal_target(void)
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return;
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conf = lapic->chip_info;
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/* Set TCC activaiton offset if supported */
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/* Set TCC activation offset if supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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@ -39,7 +39,7 @@
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#include "chip.h"
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/*
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* List of suported C-states in this processor
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* List of supported C-states in this processor
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*
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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@ -374,7 +374,7 @@ static void configure_thermal_target(void)
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return;
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conf = lapic->chip_info;
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/* Set TCC activaiton offset if supported */
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/* Set TCC activation offset if supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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@ -34,7 +34,7 @@
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*/
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/* This code is ported from coreboot v1.
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* The L2 cache initalization sequence here only apply to SECC/SECC2 P6 family
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* The L2 cache initialization sequence here only apply to SECC/SECC2 P6 family
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* CPUs with Klamath (63x), Deschutes (65x) and Katmai (67x) cores.
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* It is not required for Coppermine (68x) and Tualatin (6bx) cores.
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* It is currently not known if Celerons with Mendocino (66x) core require the
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@ -295,7 +295,7 @@ int write_l2(u32 address, u32 data)
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// data1 = ffffffff
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// data2 = 000000dc
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// address = 00aaaaaa
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// Final address signalled:
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// Final address signaled:
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// 000fffff fff000c0 000dcaaa aaa00000
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data1 = data & 0xff;
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data1 = data1 << 21;
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@ -343,7 +343,7 @@ int test_l2_address_alias(u32 address1, u32 address2,
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/* Calculates the L2 cache size.
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*
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* Reference: Intel(R) 64 and IA-32 Architectures Software Developer’s Manual
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* Reference: Intel(R) 64 and IA-32 Architectures Software Developer<EFBFBD>s Manual
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* Volume 3B: System Programming Guide, Part 2, Intel pub. 253669, pg. B-172.
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*
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*/
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@ -72,7 +72,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
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#define MCT_HZ 24000000
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/*
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* Set mshci controller instances clock drivder
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* Set mshci controller instances clock divider
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*
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* @param enum periph_id instance of the mshci controller
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*
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@ -521,7 +521,7 @@ struct exynos5_mct_regs {
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};
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#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
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#define EPLL_SRC_CLOCK 24000000 /*24 MHz Cristal Input */
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#define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */
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#define TIMEOUT_EPLL_LOCK 1000
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||||
#define AUDIO_0_RATIO_MASK 0x0f
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
|
|||
{24, 1, 20, -1}, /* PERIPH_ID_SATA */
|
||||
};
|
||||
|
||||
/* Epll Clock division values to achive different frequency output */
|
||||
/* Epll Clock division values to achieve different frequency output */
|
||||
static struct st_epll_con_val epll_div[] = {
|
||||
{ 192000000, 0, 48, 3, 1, 0 },
|
||||
{ 180000000, 0, 45, 3, 1, 0 },
|
||||
|
|
@ -405,7 +405,7 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
|
|||
u32 *reg;
|
||||
|
||||
/*
|
||||
* For now we only handle a very small subset of peipherals here.
|
||||
* For now we only handle a very small subset of peripherals here.
|
||||
* Others will need to (and do) mangle the clock registers
|
||||
* themselves, At some point it is hoped that this function can work
|
||||
* from a table or calculated register offset / mask. For now this
|
||||
|
|
@ -636,7 +636,7 @@ int clock_epll_set_rate(unsigned long rate)
|
|||
epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
|
||||
|
||||
/*
|
||||
* Required period ( in cycles) to genarate a stable clock output.
|
||||
* Required period ( in cycles) to generate a stable clock output.
|
||||
* The maximum clock time can be up to 3000 * PDIV cycles of PLLs
|
||||
* frequency input (as per spec)
|
||||
*/
|
||||
|
|
@ -675,7 +675,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
|
|||
unsigned int div ;
|
||||
|
||||
if ((dst_frq == 0) || (src_frq == 0)) {
|
||||
printk(BIOS_DEBUG, "%s: Invalid requency input for prescaler\n", __func__);
|
||||
printk(BIOS_DEBUG, "%s: Invalid frequency input for prescaler\n", __func__);
|
||||
printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
|
||||
return -1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ static void exynos_displayport_init(device_t dev)
|
|||
*
|
||||
* Note: We may want to do something clever to ensure the framebuffer
|
||||
* region is aligned such that we don't change dcache policy for other
|
||||
* stuff inadvertantly.
|
||||
* stuff inadvertently.
|
||||
*/
|
||||
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
|
||||
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
|
||||
|
|
|
|||
|
|
@ -328,7 +328,7 @@ struct mem_timings {
|
|||
uint8_t chips_per_channel; /* number of chips per channel */
|
||||
uint8_t chips_to_configure; /* number of chips to configure */
|
||||
uint8_t send_zq_init; /* 1 to send this command */
|
||||
unsigned int impedance; /* drive strength impedeance */
|
||||
unsigned int impedance; /* drive strength impedance */
|
||||
uint8_t gate_leveling_enable; /* check gate leveling is enabled */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ int dmc_config_zq(struct mem_timings *mem,
|
|||
val &= ~ZQ_MANUAL_STR;
|
||||
|
||||
/*
|
||||
* Since we are manaully calibrating the ZQ values,
|
||||
* Since we are manually calibrating the ZQ values,
|
||||
* we are looping for the ZQ_init to complete.
|
||||
*/
|
||||
i = ZQ_INIT_TIMEOUT;
|
||||
|
|
@ -97,12 +97,12 @@ void update_reset_dll(struct exynos5_dmc *dmc, enum ddr_mode mode)
|
|||
writel(val, &dmc->phycontrol0);
|
||||
}
|
||||
|
||||
/* Update DLL Information: Force DLL Resyncronization */
|
||||
/* Update DLL Information: Force DLL Resynchronization */
|
||||
val = readl(&dmc->phycontrol0);
|
||||
val |= FP_RSYNC;
|
||||
writel(val, &dmc->phycontrol0);
|
||||
|
||||
/* Reset Force DLL Resyncronization */
|
||||
/* Reset Force DLL Resynchronization */
|
||||
val = readl(&dmc->phycontrol0);
|
||||
val &= ~FP_RSYNC;
|
||||
writel(val, &dmc->phycontrol0);
|
||||
|
|
|
|||
|
|
@ -139,9 +139,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
|
||||
&dmc->concontrol);
|
||||
|
||||
/* Memory Channel Inteleaving Size */
|
||||
/* Memory Channel Interleaving Size */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Memory Channel Inteleaving Size\n");
|
||||
"Memory Channel Interleaving Size\n");
|
||||
writel(mem->iv_size, &dmc->ivcontrol);
|
||||
|
||||
/* Set DMC MEMCONTROL register */
|
||||
|
|
@ -161,7 +161,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
|
|||
|
||||
/* Power Down mode Configuration */
|
||||
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: "
|
||||
"Power Down mode Configuraation\n");
|
||||
"Power Down mode Configuration\n");
|
||||
writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
|
||||
mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
|
||||
&dmc->pwrdnconfig);
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#define MAX_CR_LOOP 5
|
||||
#define MAX_EQ_LOOP 4
|
||||
|
||||
/* Link tare type */
|
||||
/* Link rate type */
|
||||
enum link_rate {
|
||||
LINK_RATE_1_62GBPS = 0x06,
|
||||
LINK_RATE_2_70GBPS = 0x0a
|
||||
|
|
@ -126,7 +126,7 @@ struct s5p_dp_device {
|
|||
*/
|
||||
void s5p_dp_reset(struct s5p_dp_device *dp);
|
||||
/*
|
||||
* Initialize DP to recieve video stream
|
||||
* Initialize DP to receive video stream
|
||||
*
|
||||
* param dp pointer to main s5p-dp structure
|
||||
*/
|
||||
|
|
@ -214,8 +214,8 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp);
|
|||
*
|
||||
* param dp pointer to main s5p-dp structure
|
||||
* param type clock_recovery_m_value_type
|
||||
* param m_value to caluculate m_vid value
|
||||
* param n_value to caluculate n_vid value
|
||||
* param m_value to calculate m_vid value
|
||||
* param n_value to calculate n_vid value
|
||||
*/
|
||||
void s5p_dp_set_video_cr_mn(struct s5p_dp_device *dp,
|
||||
enum clock_recovery_m_value_type type,
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ void s5p_dp_reset(struct s5p_dp_device *dp)
|
|||
/* Set interrupt pin assertion polarity as high */
|
||||
writel(INT_POL0 | INT_POL1, &base->int_ctl);
|
||||
|
||||
/* Clear pending regisers */
|
||||
/* Clear pending registers */
|
||||
writel(0xff, &base->common_int_sta_1);
|
||||
writel(0x4f, &base->common_int_sta_2);
|
||||
writel(0xe0, &base->common_int_sta_3);
|
||||
|
|
@ -156,7 +156,7 @@ void s5p_dp_init_aux(struct s5p_dp_device *dp)
|
|||
u32 reg;
|
||||
struct exynos5_dp *base = dp->base;
|
||||
|
||||
/* Clear inerrupts related to AUX channel */
|
||||
/* Clear interrupts related to AUX channel */
|
||||
reg = RPLY_RECEIV | AUX_ERR;
|
||||
writel(reg, &base->dp_int_sta);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,11 +86,11 @@ struct exynos5_fimd_panel {
|
|||
unsigned int upper_margin; /* Vertical Backporch */
|
||||
unsigned int lower_margin; /* Vertical frontporch */
|
||||
unsigned int vsync; /* Vertical Sync Pulse Width */
|
||||
unsigned int left_margin; /* Horizantal Backporch */
|
||||
unsigned int left_margin; /* Horizontal Backporch */
|
||||
unsigned int right_margin; /* Horizontal Frontporch */
|
||||
unsigned int hsync; /* Horizontal Sync Pulse Width */
|
||||
unsigned int xres; /* X Resolution */
|
||||
unsigned int yres; /* Y Resopultion */
|
||||
unsigned int yres; /* Y Resolution */
|
||||
};
|
||||
|
||||
/* LCDIF Register Map */
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ void exynos_pinmux_sdmmc2(void)
|
|||
void exynos_pinmux_sdmmc3(void)
|
||||
{
|
||||
/*
|
||||
* TODO: Need to add defintions for GPC4 before
|
||||
* TODO: Need to add definitions for GPC4 before
|
||||
* enabling this.
|
||||
*/
|
||||
printk(BIOS_DEBUG, "SDMMC3 not supported yet");
|
||||
|
|
|
|||
|
|
@ -661,7 +661,7 @@ struct exynos5_phy_control;
|
|||
#define MEM_TERM_EN (1 << 31) /* Termination enable for memory */
|
||||
#define PHY_TERM_EN (1 << 30) /* Termination enable for PHY */
|
||||
#define DMC_CTRL_SHGATE (1 << 29) /* Duration of DQS gating signal */
|
||||
#define FP_RSYNC (1 << 3) /* Force DLL resyncronization */
|
||||
#define FP_RSYNC (1 << 3) /* Force DLL resynchronization */
|
||||
|
||||
/* Driver strength for CK, CKE, CS & CA */
|
||||
#define IMP_OUTPUT_DRV_40_OHM 0x5
|
||||
|
|
@ -676,7 +676,7 @@ struct exynos5_phy_control;
|
|||
|
||||
struct mem_timings;
|
||||
|
||||
/* Errors that we can encourter in low-level setup */
|
||||
/* Errors that we can encounter in low-level setup */
|
||||
enum {
|
||||
SETUP_ERR_OK,
|
||||
SETUP_ERR_RDLV_COMPLETE_TIMEOUT = -1,
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ static void exynos_spi_rx_tx(struct exynos_spi *regs, int todo,
|
|||
unsigned int *rxp = (unsigned int *)(dinp + (i * (32 * 1024)));
|
||||
unsigned int out_bytes, in_bytes;
|
||||
|
||||
// TODO In currrent implementation, every read/write must be aligned to
|
||||
// TODO In current implementation, every read/write must be aligned to
|
||||
// 4 bytes, otherwise you may get timeout or other unexpected results.
|
||||
ASSERT(todo % 4 == 0);
|
||||
|
||||
|
|
@ -90,7 +90,7 @@ int exynos_spi_open(struct exynos_spi *regs)
|
|||
SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
|
||||
clrbits_le32(®s->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
|
||||
|
||||
/* clear rx and tx channel if set priveously */
|
||||
/* clear rx and tx channel if set previously */
|
||||
clrbits_le32(®s->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
|
||||
|
||||
setbits_le32(®s->swap_cfg,
|
||||
|
|
|
|||
|
|
@ -69,8 +69,8 @@ struct tmu_info exynos5250_tmu_info = {
|
|||
|
||||
/*
|
||||
* After reading temperature code from register, compensating
|
||||
* its value and calculating celsius temperatue,
|
||||
* get current temperatue.
|
||||
* its value and calculating celsius temperature,
|
||||
* get current temperature.
|
||||
*
|
||||
* @return current temperature of the chip as sensed by TMU
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ enum tmu_status_t {
|
|||
TMU_STATUS_TRIPPED,
|
||||
};
|
||||
|
||||
/* Tmeperature threshold values for various thermal events */
|
||||
/* Temperature threshold values for various thermal events */
|
||||
struct temperature_params {
|
||||
/* minimum value in temperature code range */
|
||||
unsigned int min_val;
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
|
|||
* The coefficient, used to calculate the baudrate on S5P UARTs is
|
||||
* calculated as
|
||||
* C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
|
||||
* however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
|
||||
* however, section 31.6.11 of the datasheet doesn't recommend using 1 for 1,
|
||||
* 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
|
||||
*/
|
||||
static const int udivslot[] = {
|
||||
|
|
@ -129,7 +129,7 @@ static int exynos5_uart_err_check(int op)
|
|||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* otherwise. When the function is successful, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
static unsigned char exynos5_uart_rx_byte(void)
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@ static void am335x_uart_init_dev(void)
|
|||
|
||||
/*
|
||||
* Read a single byte from the serial port. Returns 1 on success, 0
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* otherwise. When the function is successful, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
static unsigned char am335x_uart_rx_byte(void)
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ struct am335x_uart {
|
|||
uint8_t rsvd_0x36[2];
|
||||
uint16_t blr; /* BOF control */
|
||||
uint8_t rsvd_0x3a[2];
|
||||
uint16_t acreg; /* auxilliary control */
|
||||
uint16_t acreg; /* auxiliary control */
|
||||
uint8_t rsvd_0x3e[2];
|
||||
|
||||
/* 0x40 */
|
||||
|
|
@ -139,7 +139,7 @@ struct am335x_uart {
|
|||
uint16_t ssr; /* supplementary status */
|
||||
uint8_t rsvd_0x46[2];
|
||||
|
||||
uint16_t eblr; /* BOF length (operatoinal mode only) */
|
||||
uint16_t eblr; /* BOF length (operational mode only) */
|
||||
uint8_t rsvd_0x4a[6];
|
||||
|
||||
/* 0x50 */
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
|
|||
msr.hi = 0;
|
||||
wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);
|
||||
|
||||
/* Let's see if we updated succesfully */
|
||||
/* Let's see if we updated successfully */
|
||||
msr = rdmsr(MSR_UCODE_UPDATE_STATUS);
|
||||
|
||||
return msr.lo & 0x07;
|
||||
|
|
@ -80,7 +80,7 @@ static void nano_print_ucode_status(ucode_update_status stat)
|
|||
switch(stat)
|
||||
{
|
||||
case UCODE_UPDATE_SUCCESS:
|
||||
printk(BIOS_INFO, "Microcode update succesful.\n");
|
||||
printk(BIOS_INFO, "Microcode update successful.\n");
|
||||
break;
|
||||
case UCODE_UPDATE_FAIL:
|
||||
printk(BIOS_ALERT, "Microcode update failed, bad environment."
|
||||
|
|
|
|||
|
|
@ -56,11 +56,11 @@ typedef struct {
|
|||
u32 applicable_fms; /* Fam/model/stepping to which ucode applies */
|
||||
u32 checksum; /* Two's complement checksum of ucode+header */
|
||||
u32 loader_revision; /* Revision of hardware ucode update loader*/
|
||||
u32 rfu_1; /* Reservod for future use */
|
||||
u32 rfu_1; /* Reserved for future use */
|
||||
u32 payload_size; /* Size of the ucode payload only */
|
||||
u32 total_size; /* Size of the ucode, including header */
|
||||
char name[8]; /* ASCII string of ucode filename */
|
||||
u32 rfu_2; /* Reservod for future use */
|
||||
u32 rfu_2; /* Reserved for future use */
|
||||
/* First double-word of the ucode payload
|
||||
* Its address represents the beginning of the ucode update we need to
|
||||
* send to the CPU */
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ extern char _car_data_end[];
|
|||
|
||||
/*
|
||||
* The car_migrated global variable determines if the cache-as-ram space has
|
||||
* been migrated to real RAM. It does this by asumming the following things:
|
||||
* been migrated to real RAM. It does this by assuming the following things:
|
||||
* 1. cache-as-ram space is zero'd out once it is set up.
|
||||
* 2. Either the cache-as-ram space is memory-backed after getting torn down
|
||||
* or the space returns 0xff's for each byte read.
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
* will return 0, meaning no CPU.
|
||||
*
|
||||
* We actually handling that case by noting which cpus startup
|
||||
* and not telling anyone about the ones that dont.
|
||||
* and not telling anyone about the ones that don't.
|
||||
*/
|
||||
|
||||
/* Start-UP IPI vector must be 4kB aligned and below 1MB. */
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ static void cache_ramstage(void)
|
|||
const int addr_det = 0;
|
||||
|
||||
/* the fixed and variable MTTRs are power-up with random values,
|
||||
* clear them to MTRR_TYPE_UNCACHEABLE for safty.
|
||||
* clear them to MTRR_TYPE_UNCACHEABLE for safety.
|
||||
*/
|
||||
static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
|
||||
{
|
||||
|
|
@ -43,7 +43,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
|
|||
msr_t msr;
|
||||
const unsigned long *msr_addr;
|
||||
|
||||
/* Inialize all of the relevant msrs to 0 */
|
||||
/* Initialize all of the relevant msrs to 0 */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
unsigned long msr_nr;
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ static inline unsigned int fms(unsigned int x)
|
|||
return r;
|
||||
}
|
||||
|
||||
/* fls: find least sigificant bit set */
|
||||
/* fls: find least significant bit set */
|
||||
static inline unsigned int fls(unsigned int x)
|
||||
{
|
||||
int r;
|
||||
|
|
@ -160,8 +160,8 @@ static struct memranges *get_physical_address_space(void)
|
|||
static struct memranges addr_space_storage;
|
||||
|
||||
/* In order to handle some chipsets not being able to pre-determine
|
||||
* uncacheable ranges, such as graphics memory, at resource inseration
|
||||
* time remove unacheable regions from the cacheable ones. */
|
||||
* uncacheable ranges, such as graphics memory, at resource insertion
|
||||
* time remove uncacheable regions from the cacheable ones. */
|
||||
if (addr_space == NULL) {
|
||||
struct range_entry *r;
|
||||
unsigned long mask;
|
||||
|
|
@ -216,7 +216,7 @@ static struct memranges *get_physical_address_space(void)
|
|||
}
|
||||
|
||||
/* Fixed MTRR descriptor. This structure defines the step size and begin
|
||||
* and end (exclusive) address covered by a set of fixe MTRR MSRs.
|
||||
* and end (exclusive) address covered by a set of fixed MTRR MSRs.
|
||||
* It also describes the offset in byte intervals to store the calculated MTRR
|
||||
* type in an array. */
|
||||
struct fixed_mtrr_desc {
|
||||
|
|
@ -533,7 +533,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
|
|||
struct range_entry *next;
|
||||
|
||||
/*
|
||||
* Determine MTRRs based on the following algoirthm for the given entry:
|
||||
* Determine MTRRs based on the following algorithm for the given entry:
|
||||
* +------------------+ b2 = ALIGN_UP(end)
|
||||
* | 0 or more bytes | <-- hole is carved out between b1 and b2
|
||||
* +------------------+ a2 = b1 = end
|
||||
|
|
@ -571,7 +571,7 @@ static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state,
|
|||
|
||||
b1 = a2;
|
||||
|
||||
/* First check if a1 is >= 4GiB and the current etnry is the last
|
||||
/* First check if a1 is >= 4GiB and the current entry is the last
|
||||
* entry. If so perform an optimization of covering a larger range
|
||||
* defined by the base address' alignment. */
|
||||
if (a1 >= RANGE_4GB && next == NULL) {
|
||||
|
|
@ -686,10 +686,10 @@ static int calc_var_mtrrs(struct memranges *addr_space,
|
|||
* 1. UC as default type with no holes at top of range.
|
||||
* 2. UC as default using holes at top of range.
|
||||
* 3. WB as default.
|
||||
* The lowest count is then used as default after totalling all
|
||||
* MTRRs. Note that the optimal algoirthm for UC default is marked in
|
||||
* The lowest count is then used as default after totaling all
|
||||
* MTRRs. Note that the optimal algorithm for UC default is marked in
|
||||
* the tag of each range regardless of final decision. UC takes
|
||||
* precedence in the MTRR archiecture. Therefore, only holes can be
|
||||
* precedence in the MTRR architecture. Therefore, only holes can be
|
||||
* used when the type of the region is MTRR_TYPE_WRBACK with
|
||||
* MTRR_TYPE_UNCACHEABLE as the default type.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -24,16 +24,16 @@
|
|||
#include <console/console.h>
|
||||
|
||||
/*
|
||||
* Compoments that make up the SMRAM:
|
||||
* Components that make up the SMRAM:
|
||||
* 1. Save state - the total save state memory used
|
||||
* 2. Stack - stacks for the CPUs in the SMM handler
|
||||
* 3. Stub - SMM stub code for calling into handler
|
||||
* 4. Handler - C-based SMM handler.
|
||||
*
|
||||
* The compoents are assumed to consist of one consecutive region.
|
||||
* The components are assumed to consist of one consecutive region.
|
||||
*/
|
||||
|
||||
/* These paramters are used by the SMM stub code. A pointer to the params
|
||||
/* These parameters are used by the SMM stub code. A pointer to the params
|
||||
* is also passed to the C-base handler. */
|
||||
struct smm_stub_params {
|
||||
u32 stack_size;
|
||||
|
|
@ -80,7 +80,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num,
|
|||
|
||||
/* Each entry point has an IP value of 0x8000. The SMBASE for each
|
||||
* cpu is different so the effective address of the entry instruction
|
||||
* is different. Therefore, the relative displacment for each entry
|
||||
* is different. Therefore, the relative displacement for each entry
|
||||
* instruction needs to be updated to reflect the current effective
|
||||
* IP. Additionally, the IP result from the jmp instruction is
|
||||
* calculated using the next instruction's address so the size of
|
||||
|
|
@ -140,7 +140,7 @@ static void smm_stub_place_staggered_entry_points(char *base,
|
|||
stub_entry_offset = rmodule_entry_offset(smm_stub);
|
||||
|
||||
/* If there are staggered entry points or the stub is not located
|
||||
* at the SMM entry point then jmp instructionss need to be placed. */
|
||||
* at the SMM entry point then jmp instructions need to be placed. */
|
||||
if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) {
|
||||
int num_entries;
|
||||
|
||||
|
|
@ -297,7 +297,7 @@ int smm_setup_relocation_handler(struct smm_loader_params *params)
|
|||
return -1;
|
||||
|
||||
/* Since the relocation handler always uses stack, adjust the number
|
||||
* of conccurent stack users to be CONFIG_MAX_CPUS. */
|
||||
* of concurrent stack users to be CONFIG_MAX_CPUS. */
|
||||
if (params->num_concurrent_stacks == 0)
|
||||
params->num_concurrent_stacks = CONFIG_MAX_CPUS;
|
||||
|
||||
|
|
@ -318,7 +318,7 @@ int smm_setup_relocation_handler(struct smm_loader_params *params)
|
|||
*
|
||||
* It should be noted that this algorithm will not work for
|
||||
* SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm
|
||||
* expectes a region large enough to encompass the handler and stacks
|
||||
* expects a region large enough to encompass the handler and stacks
|
||||
* as well as the SMM_DEFAULT_SIZE.
|
||||
*/
|
||||
int smm_load_module(void *smram, int size, struct smm_loader_params *params)
|
||||
|
|
|
|||
Loading…
Reference in New Issue