nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically
Computes TSEG size dynamically. Changes the size of legacy hole to match other Intel northbirdges. Refactor this a little by needing one less variable. Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -29,20 +29,19 @@
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#include <northbridge/intel/x4x/chip.h>
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#include <northbridge/intel/x4x/chip.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <northbridge/intel/x4x/x4x.h>
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static void mch_domain_read_resources(device_t dev)
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static void mch_domain_read_resources(device_t dev)
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{
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{
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u8 index;
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u8 index, reg8;
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u64 tom, touud;
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u64 tom, touud;
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u32 tomk, tseg_sizek, tolud, usable_tomk;
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u32 tomk, tseg_sizek = 0, tolud;
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u32 pcie_config_base, pcie_config_size;
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u32 pcie_config_base, pcie_config_size;
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u32 uma_sizek = 0;
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u32 uma_sizek = 0;
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const u32 top32memk = 4 * (GiB / KiB);
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const u32 top32memk = 4 * (GiB / KiB);
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index = 3;
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index = 3;
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/* 1024KiB TSEG */
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tseg_sizek = 1024;
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pci_domain_read_resources(dev);
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pci_domain_read_resources(dev);
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/* Top of Upper Usable DRAM, including remap */
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/* Top of Upper Usable DRAM, including remap */
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@ -63,25 +62,51 @@ static void mch_domain_read_resources(device_t dev)
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tomk = tolud >> 10;
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tomk = tolud >> 10;
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/* Graphics memory comes next */
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/* Graphics memory comes next */
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const u16 ggc = pci_read_config16(dev, D0F0_GGC);
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const u16 ggc = pci_read_config16(dev, D0F0_GGC);
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printk(BIOS_DEBUG, "IGD decoded, subtracting ");
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printk(BIOS_DEBUG, "IGD decoded, subtracting ");
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/* Graphics memory */
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/* Graphics memory */
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const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
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const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
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printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
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printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
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tomk -= gms_sizek;
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uma_sizek += gms_sizek;
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/* GTT Graphics Stolen Memory Size (GGMS) */
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/* GTT Graphics Stolen Memory Size (GGMS) */
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const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
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const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
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printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
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printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
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tomk -= gsm_sizek;
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uma_sizek += gsm_sizek;
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uma_sizek = gms_sizek + gsm_sizek + tseg_sizek;
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printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
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usable_tomk = tomk - uma_sizek;
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reg8 = pci_read_config8(dev, D0F0_ESMRAMC);
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reg8 >>= 1;
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reg8 &= 3;
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switch (reg8) {
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case 0:
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tseg_sizek = 1024;
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break; /* TSEG = 1M */
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case 1:
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tseg_sizek = 2048;
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break; /* TSEG = 2M */
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case 2:
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tseg_sizek = 8192;
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break; /* TSEG = 8M */
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}
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uma_sizek += tseg_sizek;
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tomk -= tseg_sizek;
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printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
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printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10);
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printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
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/* Report the memory regions */
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/* Report the memory regions */
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ram_resource(dev, index++, 0, 0xa0000 >> 10);
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ram_resource(dev, index++, 0, legacy_hole_base_k);
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ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10)));
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mmio_resource(dev, index++, legacy_hole_base_k,
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(0xc0000 >> 10) - legacy_hole_base_k);
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reserved_ram_resource(dev, index++, 0xc0000 >> 10,
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(0x100000 - 0xc0000) >> 10);
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ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
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/*
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/*
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* If >= 4GB installed then memory from TOLUD to 4GB
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* If >= 4GB installed then memory from TOLUD to 4GB
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@ -95,9 +120,8 @@ static void mch_domain_read_resources(device_t dev)
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}
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}
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printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "
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printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "
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"size=0x%08x\n", usable_tomk << 10, uma_sizek << 10);
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"size=0x%08x\n", tomk << 10, uma_sizek << 10);
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fixed_mem_resource(dev, index++, usable_tomk, uma_sizek,
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uma_resource(dev, index++, tomk, uma_sizek);
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IORESOURCE_RESERVE);
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/* Reserve high memory where the NB BARs are up to 4GiB */
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/* Reserve high memory where the NB BARs are up to 4GiB */
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fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
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fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
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