move default_resource_map to its own file
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
f76a613a9a
commit
4c5060dc2b
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@ -99,7 +99,6 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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maxnodes=2;
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}
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if (!(node>=maxnodes || row>=maxnodes)) {
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ret=rows_2p[node][row];
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}
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@ -120,6 +119,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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@ -101,6 +101,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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static void enable_lapic(void)
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{
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@ -259,10 +259,10 @@ northbridge amd/amdk8 "mc0"
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 2
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#pci 0:0.0
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#pci 0:0.1
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#pci 0:1.0
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#pci 0:1.1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 2
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#pci 0:0.0
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@ -119,10 +119,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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}
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "mainboard/amd/serenade/resourcemap.c"
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#include "resourcemap.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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@ -88,6 +88,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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static void main(void)
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{
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@ -92,6 +92,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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uint32_t ret = 0x00010101; /* default row entry */
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/* CPU0 LDT1 <-> LDT1 CPU1 */
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static const unsigned int rows_2p[2][2] = {
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{ 0x00050101, 0x00010404 },
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{ 0x00010404, 0x00050101 }
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@ -102,7 +103,6 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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maxnodes = 2;
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}
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if (!(node >= maxnodes || row >= maxnodes)) {
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ret = rows_2p[node][row];
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}
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@ -123,6 +123,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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@ -173,6 +174,7 @@ static void main(void)
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setup_default_resource_map();
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needs_reset = setup_coherent_ht_domain();
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/* Non-coherent HT is on LDT0 */
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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@ -14,7 +14,7 @@ static void setup_resource_map(const unsigned int *register_values, int max)
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#if 0
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print_debug("\r\n");
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#endif
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for(i = 0; i < max; i += 3) {
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for (i = 0; i < max; i += 3) {
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device_t dev;
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unsigned where;
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unsigned long reg;
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@ -40,265 +40,6 @@ static void setup_resource_map(const unsigned int *register_values, int max)
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print_debug("done.\r\n");
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}
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static void setup_default_resource_map(void)
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{
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static const unsigned int register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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* F1:0x54 i = 2
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* F1:0x5C i = 3
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* F1:0x64 i = 4
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* F1:0x6C i = 5
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* F1:0x74 i = 6
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* F1:0x7C i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 3] Reserved
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* [10: 8] Interleave select
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* specifies the values of A[14:12] to use with interleave enable.
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* [15:11] Reserved
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* [31:16] DRAM Limit Address i Bits 39-24
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* This field defines the upper address bits of a 40 bit address
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* that define the end of the DRAM region.
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*/
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PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
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PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
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PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
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PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
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PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
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PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
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PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
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/* DRAM Base i Registers
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* F1:0x40 i = 0
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* F1:0x48 i = 1
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* F1:0x50 i = 2
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* F1:0x58 i = 3
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* F1:0x60 i = 4
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* F1:0x68 i = 5
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* F1:0x70 i = 6
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* F1:0x78 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 7: 2] Reserved
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* [10: 8] Interleave Enable
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* 000 = No interleave
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* 001 = Interleave on A[12] (2 nodes)
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* 010 = reserved
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* 011 = Interleave on A[12] and A[14] (4 nodes)
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* 100 = reserved
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* 101 = reserved
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* 110 = reserved
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* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
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* [15:11] Reserved
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* [13:16] DRAM Base Address i Bits 39-24
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* This field defines the upper address bits of a 40-bit address
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* that define the start of the DRAM region.
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*/
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PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
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/* Memory-Mapped I/O Limit i Registers
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* F1:0x84 i = 0
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* F1:0x8C i = 1
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* F1:0x94 i = 2
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* F1:0x9C i = 3
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* F1:0xA4 i = 4
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* F1:0xAC i = 5
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* F1:0xB4 i = 6
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* F1:0xBC i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 3: 3] Reserved
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* [ 5: 4] Destination Link ID
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 = Reserved
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* [ 6: 6] Reserved
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* [ 7: 7] Non-Posted
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* 0 = CPU writes may be posted
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* 1 = CPU writes must be non-posted
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* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
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* This field defines the upp adddress bits of a 40-bit address that
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* defines the end of a memory-mapped I/O region n
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*/
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PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
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/* Memory-Mapped I/O Base i Registers
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* F1:0x80 i = 0
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* F1:0x88 i = 1
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* F1:0x90 i = 2
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* F1:0x98 i = 3
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* F1:0xA0 i = 4
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* F1:0xA8 i = 5
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* F1:0xB0 i = 6
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* F1:0xB8 i = 7
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* [ 0: 0] Read Enable
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* 0 = Reads disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes disabled
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* 1 = Writes Enabled
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* [ 2: 2] Cpu Disable
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* 0 = Cpu can use this I/O range
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* 1 = Cpu requests do not use this I/O range
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* [ 3: 3] Lock
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* 0 = base/limit registers i are read/write
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* 1 = base/limit registers i are read-only
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* [ 7: 4] Reserved
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* [31: 8] Memory-Mapped I/O Base Address i (39-16)
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* This field defines the upper address bits of a 40bit address
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* that defines the start of memory-mapped I/O region i
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*/
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PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
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/* PCI I/O Limit i Registers
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* F1:0xC4 i = 0
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* F1:0xCC i = 1
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* F1:0xD4 i = 2
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* F1:0xDC i = 3
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 3: 3] Reserved
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* [ 5: 4] Destination Link ID
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 = reserved
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* [11: 6] Reserved
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* [24:12] PCI I/O Limit Address i
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* This field defines the end of PCI I/O region n
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* [31:25] Reserved
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*/
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PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
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PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
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/* PCI I/O Base i Registers
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* F1:0xC0 i = 0
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* F1:0xC8 i = 1
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* F1:0xD0 i = 2
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* F1:0xD8 i = 3
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 3: 2] Reserved
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* [ 4: 4] VGA Enable
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* 0 = VGA matches Disabled
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* 1 = matches all address < 64K and where A[9:0] is in the
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* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
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* [ 5: 5] ISA Enable
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* 0 = ISA matches Disabled
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* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
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* from matching agains this base/limit pair
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* [11: 6] Reserved
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* [24:12] PCI I/O Base i
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* This field defines the start of PCI I/O region n
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* [31:25] Reserved
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*/
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PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
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PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
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/* Config Base and Limit i Registers
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* F1:0xE0 i = 0
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* F1:0xE4 i = 1
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* F1:0xE8 i = 2
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* F1:0xEC i = 3
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* [ 0: 0] Read Enable
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* 0 = Reads Disabled
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* 1 = Reads Enabled
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* [ 1: 1] Write Enable
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* 0 = Writes Disabled
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* 1 = Writes Enabled
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* [ 2: 2] Device Number Compare Enable
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* 0 = The ranges are based on bus number
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* 1 = The ranges are ranges of devices on bus 0
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* [ 3: 3] Reserved
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* [ 6: 4] Destination Node
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 7] Reserved
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* [ 9: 8] Destination Link
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* 00 = Link 0
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* 01 = Link 1
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* 10 = Link 2
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* 11 - Reserved
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* [15:10] Reserved
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* [23:16] Bus Number Base i
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* This field defines the lowest bus number in configuration region i
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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*/
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PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
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PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
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};
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int max;
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max = sizeof(register_values)/sizeof(register_values[0]);
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setup_resource_map(register_values, max);
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}
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static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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static const unsigned int register_values[] = {
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@ -0,0 +1,258 @@
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static void setup_default_resource_map(void)
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{
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static const unsigned int register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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* F1:0x54 i = 2
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* F1:0x5C i = 3
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* F1:0x64 i = 4
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* F1:0x6C i = 5
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* F1:0x74 i = 6
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* F1:0x7C i = 7
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* [ 2: 0] Destination Node ID
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* 000 = Node 0
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* 001 = Node 1
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* 010 = Node 2
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* 011 = Node 3
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* 100 = Node 4
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* 101 = Node 5
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* 110 = Node 6
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* 111 = Node 7
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* [ 7: 3] Reserved
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* [10: 8] Interleave select
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* specifies the values of A[14:12] to use with interleave enable.
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* [15:11] Reserved
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* [31:16] DRAM Limit Address i Bits 39-24
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* This field defines the upper address bits of a 40 bit address
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* that define the end of the DRAM region.
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*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||
/* DRAM Base i Registers
|
||||
* F1:0x40 i = 0
|
||||
* F1:0x48 i = 1
|
||||
* F1:0x50 i = 2
|
||||
* F1:0x58 i = 3
|
||||
* F1:0x60 i = 4
|
||||
* F1:0x68 i = 5
|
||||
* F1:0x70 i = 6
|
||||
* F1:0x78 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 7: 2] Reserved
|
||||
* [10: 8] Interleave Enable
|
||||
* 000 = No interleave
|
||||
* 001 = Interleave on A[12] (2 nodes)
|
||||
* 010 = reserved
|
||||
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||
* 100 = reserved
|
||||
* 101 = reserved
|
||||
* 110 = reserved
|
||||
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||
* [15:11] Reserved
|
||||
* [13:16] DRAM Base Address i Bits 39-24
|
||||
* This field defines the upper address bits of a 40-bit address
|
||||
* that define the start of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||
|
||||
/* Memory-Mapped I/O Limit i Registers
|
||||
* F1:0x84 i = 0
|
||||
* F1:0x8C i = 1
|
||||
* F1:0x94 i = 2
|
||||
* F1:0x9C i = 3
|
||||
* F1:0xA4 i = 4
|
||||
* F1:0xAC i = 5
|
||||
* F1:0xB4 i = 6
|
||||
* F1:0xBC i = 7
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = Reserved
|
||||
* [ 6: 6] Reserved
|
||||
* [ 7: 7] Non-Posted
|
||||
* 0 = CPU writes may be posted
|
||||
* 1 = CPU writes must be non-posted
|
||||
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||
* This field defines the upp adddress bits of a 40-bit address that
|
||||
* defines the end of a memory-mapped I/O region n
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
|
||||
|
||||
/* Memory-Mapped I/O Base i Registers
|
||||
* F1:0x80 i = 0
|
||||
* F1:0x88 i = 1
|
||||
* F1:0x90 i = 2
|
||||
* F1:0x98 i = 3
|
||||
* F1:0xA0 i = 4
|
||||
* F1:0xA8 i = 5
|
||||
* F1:0xB0 i = 6
|
||||
* F1:0xB8 i = 7
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Cpu Disable
|
||||
* 0 = Cpu can use this I/O range
|
||||
* 1 = Cpu requests do not use this I/O range
|
||||
* [ 3: 3] Lock
|
||||
* 0 = base/limit registers i are read/write
|
||||
* 1 = base/limit registers i are read-only
|
||||
* [ 7: 4] Reserved
|
||||
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||
|
||||
/* PCI I/O Limit i Registers
|
||||
* F1:0xC4 i = 0
|
||||
* F1:0xCC i = 1
|
||||
* F1:0xD4 i = 2
|
||||
* F1:0xDC i = 3
|
||||
* [ 2: 0] Destination Node ID
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 3: 3] Reserved
|
||||
* [ 5: 4] Destination Link ID
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 = reserved
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Limit Address i
|
||||
* This field defines the end of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||
|
||||
/* PCI I/O Base i Registers
|
||||
* F1:0xC0 i = 0
|
||||
* F1:0xC8 i = 1
|
||||
* F1:0xD0 i = 2
|
||||
* F1:0xD8 i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 3: 2] Reserved
|
||||
* [ 4: 4] VGA Enable
|
||||
* 0 = VGA matches Disabled
|
||||
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||
* [ 5: 5] ISA Enable
|
||||
* 0 = ISA matches Disabled
|
||||
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||
* from matching agains this base/limit pair
|
||||
* [11: 6] Reserved
|
||||
* [24:12] PCI I/O Base i
|
||||
* This field defines the start of PCI I/O region n
|
||||
* [31:25] Reserved
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||
|
||||
/* Config Base and Limit i Registers
|
||||
* F1:0xE0 i = 0
|
||||
* F1:0xE4 i = 1
|
||||
* F1:0xE8 i = 2
|
||||
* F1:0xEC i = 3
|
||||
* [ 0: 0] Read Enable
|
||||
* 0 = Reads Disabled
|
||||
* 1 = Reads Enabled
|
||||
* [ 1: 1] Write Enable
|
||||
* 0 = Writes Disabled
|
||||
* 1 = Writes Enabled
|
||||
* [ 2: 2] Device Number Compare Enable
|
||||
* 0 = The ranges are based on bus number
|
||||
* 1 = The ranges are ranges of devices on bus 0
|
||||
* [ 3: 3] Reserved
|
||||
* [ 6: 4] Destination Node
|
||||
* 000 = Node 0
|
||||
* 001 = Node 1
|
||||
* 010 = Node 2
|
||||
* 011 = Node 3
|
||||
* 100 = Node 4
|
||||
* 101 = Node 5
|
||||
* 110 = Node 6
|
||||
* 111 = Node 7
|
||||
* [ 7: 7] Reserved
|
||||
* [ 9: 8] Destination Link
|
||||
* 00 = Link 0
|
||||
* 01 = Link 1
|
||||
* 10 = Link 2
|
||||
* 11 - Reserved
|
||||
* [15:10] Reserved
|
||||
* [23:16] Bus Number Base i
|
||||
* This field defines the lowest bus number in configuration region i
|
||||
* [31:24] Bus Number Limit i
|
||||
* This field defines the highest bus number in configuration regin i
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||
};
|
||||
int max;
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
setup_resource_map(register_values, max);
|
||||
}
|
||||
Loading…
Reference in New Issue