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vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping 

For Phoenix the lane numbers in the DXIO descriptor match the ones in
the schematic, so remove the corresponding text and the table from the
comment on the fsp_dxio_descriptor struct. Since there's no logical to
physical lane number remapping needed for the lanes in the Phoenix DXIO
descriptors, drop the 'logical' from the start_logical_lane and
end_logical_lane fields in the DXIO descriptor and rename those to
start_lane and end_lane.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-04-05 19:57:44 +02:00
parent 4eee50642f
commit 4c548919c6
4 changed files with 39 additions and 48 deletions
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36
src/mainboard/amd/birman/port_descriptors_phoenix.c
View File

@ -10,8 +10,8 @@
#define phx_mxm_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = CONFIG(ENABLE_EVAL_CARD), \
.start_logical_lane = 0, \
.end_logical_lane = 7, \
.start_lane = 0, \
.end_lane = 7, \
.device_number = 1, \
.function_number = 1, \
.link_speed_capability = GEN3, \
@ -25,8 +25,8 @@
#define phx2_mxm_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = CONFIG(ENABLE_EVAL_CARD), \
.start_logical_lane = 0, \
.end_logical_lane = 3, \
.start_lane = 0, \
.end_lane = 3, \
.device_number = 1, \
.function_number = 1, \
.link_speed_capability = GEN3, \
@ -39,8 +39,8 @@
#define phx_ssd1_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = !CONFIG(DISABLE_DT_M2), \
.start_logical_lane = 8, \
.end_logical_lane = 11, \
.start_lane = 8, \
.end_lane = 11, \
.device_number = 1, \
.function_number = 2, \
.link_speed_capability = GEN3, \
@ -54,8 +54,8 @@
#define phx2_ssd1_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 8, \
.end_logical_lane = 9, \
.start_lane = 8, \
.end_lane = 9, \
.device_number = 1, \
.function_number = 2, \
.link_speed_capability = GEN3, \
@ -68,8 +68,8 @@
#define gbe_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 12, \
.end_logical_lane = 12, \
.start_lane = 12, \
.end_lane = 12, \
.device_number = 1, \
.function_number = 3, \
.link_speed_capability = GEN3, \
@ -82,8 +82,8 @@
#define sd_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 13, \
.end_logical_lane = 13, \
.start_lane = 13, \
.end_lane = 13, \
.device_number = 2, \
.function_number = 1, \
.link_speed_capability = GEN3, \
@ -96,8 +96,8 @@
#define wwan_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 14, \
.end_logical_lane = CONFIG(WWAN01) ? 15 : 14, \
.start_lane = 14, \
.end_lane = CONFIG(WWAN01) ? 15 : 14, \
.device_number = 2, \
.function_number = 2, \
.link_speed_capability = GEN3, \
@ -110,8 +110,8 @@
#define wlan_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 15, \
.end_logical_lane = CONFIG(WLAN01) ? 14 : 15, \
.start_lane = 15, \
.end_lane = CONFIG(WLAN01) ? 14 : 15, \
.device_number = 2, \
.function_number = 3, \
.link_speed_capability = GEN3, \
@ -124,8 +124,8 @@
#define ssd0_dxio_descriptor { \
.engine_type = PCIE_ENGINE, \
.port_present = true, \
.start_logical_lane = 16, \
.end_logical_lane = 19, \
.start_lane = 16, \
.end_lane = 19, \
.device_number = 2, \
.function_number = 4, \
.link_speed_capability = GEN3, \

16
src/mainboard/amd/mayan/port_descriptors.c
View File

@ -13,8 +13,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
// MXM
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 3,
.start_lane = 0,
.end_lane = 3,
.device_number = 1,
.function_number = 1,
.link_speed_capability = GEN_MAX,
@ -33,8 +33,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
// M2 SSD0-NVME
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 19,
.start_lane = 16,
.end_lane = 19,
.device_number = 2,
.function_number = 4,
.link_speed_capability = GEN_MAX,
@ -53,8 +53,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
// X1
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 12,
.end_logical_lane = 12,
.start_lane = 12,
.end_lane = 12,
.device_number = 1,
.function_number = 3,
.link_speed_capability = GEN_MAX,
@ -72,8 +72,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = {
// DT
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 8,
.end_logical_lane = 9,
.start_lane = 8,
.end_lane = 9,
.device_number = 1,
.function_number = 2,
.link_speed_capability = GEN_MAX,

20
src/mainboard/google/myst/port_descriptors.c
View File

@ -11,8 +11,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = {
[DXIO_WWAN] = {
.engine_type = UNUSED_ENGINE,
.port_present = true,
.start_logical_lane = 13,
.end_logical_lane = 13,
.start_lane = 13,
.end_lane = 13,
.device_number = PCI_SLOT(WWAN_DEVFN),
.function_number = PCI_FUNC(WWAN_DEVFN),
.link_speed_capability = GEN3,
@ -22,8 +22,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = {
[DXIO_WLAN] = {
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 14,
.end_logical_lane = 14,
.start_lane = 14,
.end_lane = 14,
.device_number = PCI_SLOT(WLAN_DEVFN),
.function_number = PCI_FUNC(WLAN_DEVFN),
.link_speed_capability = GEN3,
@ -33,8 +33,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = {
[DXIO_SD] = {
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 15,
.end_logical_lane = 15,
.start_lane = 15,
.end_lane = 15,
.device_number = PCI_SLOT(SD_DEVFN),
.function_number = PCI_FUNC(SD_DEVFN),
.link_speed_capability = GEN1,
@ -48,8 +48,8 @@ static fsp_dxio_descriptor myst_dxio_descriptors[] = {
static const fsp_dxio_descriptor emmc_descriptor = {
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 16,
.start_lane = 16,
.end_lane = 16,
.device_number = PCI_SLOT(NVME_DEVFN),
.function_number = PCI_FUNC(NVME_DEVFN),
.link_speed_capability = GEN_MAX,
@ -60,8 +60,8 @@ static const fsp_dxio_descriptor emmc_descriptor = {
static const fsp_dxio_descriptor nvme_descriptor = {
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 19,
.start_lane = 16,
.end_lane = 19,
.device_number = PCI_SLOT(NVME_DEVFN),
.function_number = PCI_FUNC(NVME_DEVFN),
.link_speed_capability = GEN_MAX,

15
src/vendorcode/amd/fsp/phoenix/platform_descriptors.h
View File

@ -165,16 +165,7 @@ typedef struct __packed {
/*
* Phoenix DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
* bifurcation and other settings. Beware that the lane numbers in here are the
* logical and not the physical lane numbers!
*
* Phoenix DXIO logical lane to physical PCIe lane mapping:
*
* logical | physical
* ----------|------------
* PA[00:03] | GPP[03:00]
* PA[04:05] | GPP[08:09]
* PB[00:07] | GPP[12:19]
* bifurcation and other settings.
*
* Different ports mustn't overlap or be assigned to the same lane(s). Within
* ports with the same width the one with a higher start logical lane number
@ -183,8 +174,8 @@ typedef struct __packed {
*/
typedef struct __packed {
uint8_t engine_type; // See dxio_engine_type
uint8_t start_logical_lane; // Start lane of the pci device
uint8_t end_logical_lane; // End lane of the pci device
uint8_t start_lane; // Start lane of the pci device
uint8_t end_lane; // End lane of the pci device
uint8_t gpio_group_id; // GPIO number used as reset
uint32_t port_present :1; // Should be TRUE if train link
uint32_t :7;