nb/intel/x4x,sandybridge: Move romstage_handoff_init() call

Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/northbridge/intel/sandybridge/early_init.c

@@ -6,7 +6,6 @@
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <option.h>
-#include <romstage_handoff.h>
 #include <types.h>
 
 #include "sandybridge.h"
@@ -194,9 +193,7 @@ void systemagent_early_init(void)
 	start_peg_link_training();
 }
 
-void northbridge_romstage_finalize(int s3resume)
+void northbridge_romstage_finalize(void)
 {
 	MCHBAR16(SSKPD_HI) = 0xCAFE;
-
-	romstage_handoff_init(s3resume);
 }

src/northbridge/intel/sandybridge/romstage.c

@@ -4,6 +4,7 @@
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>
+#include <romstage_handoff.h>
 #include <timestamp.h>
 #include "sandybridge.h"
 #include <arch/romstage.h>
@@ -75,7 +76,9 @@ void mainboard_romstage_entry(void)
 
 	post_code(0x3d);
 
-	northbridge_romstage_finalize(s3resume);
+	northbridge_romstage_finalize();
 
 	post_code(0x3f);
+
+	romstage_handoff_init(s3resume);
 }

src/northbridge/intel/sandybridge/sandybridge.h

@@ -72,7 +72,7 @@ void intel_sandybridge_finalize_smm(void);
 void systemagent_early_init(void);
 void sandybridge_init_iommu(void);
 void sandybridge_late_initialization(void);
-void northbridge_romstage_finalize(int s3resume);
+void northbridge_romstage_finalize(void);
 void early_init_dmi(void);
 
 /* mainboard_early_init: Optional callback, run after console init but before raminit. */

src/northbridge/intel/x4x/early_init.c

@@ -10,7 +10,6 @@
 #include <option.h>
 #include "x4x.h"
 #include <console/console.h>
-#include <romstage_handoff.h>
 
 void x4x_early_init(void)
 {
@@ -216,14 +215,8 @@ static void init_dmi(void)
 	DMIBAR16(DMILCTL);
 }
 
-static void x4x_prepare_resume(int s3resume)
-{
-	romstage_handoff_init(s3resume);
-}
-
-void x4x_late_init(int s3resume)
+void x4x_late_init(void)
 {
 	init_egress();
 	init_dmi();
-	x4x_prepare_resume(s3resume);
 }

src/northbridge/intel/x4x/romstage.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <console/console.h>
+#include <romstage_handoff.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <arch/romstage.h>
 
@@ -42,7 +43,8 @@ void mainboard_romstage_entry(void)
 	mb_get_spd_map(spd_addr_map);
 	sdram_initialize(boot_path, spd_addr_map);
 
-	x4x_late_init(s3_resume);
-
+	x4x_late_init();
 	printk(BIOS_DEBUG, "x4x late init complete\n");
+
+	romstage_handoff_init(s3_resume);
 }

src/northbridge/intel/x4x/x4x.h

@@ -157,7 +157,7 @@
 #define EP_PORTARB(x)	(0x100 + 4 * (x))	/* 256bit */
 
 void x4x_early_init(void);
-void x4x_late_init(int s3resume);
+void x4x_late_init(void);
 void mb_get_spd_map(u8 spd_map[4]);
 void mb_pre_raminit_setup(int s3_resume);
 u32 decode_igd_memory_size(u32 gms);