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veyron_*: Move PMIC_BUS to a Kconfig variable 

This moves PMIC_BUS from each mainboard's board.h file to a per-
mainboard Kconfig variable. To prevent humans from forgetting to
set a valid value, an invalid default is set in the rk3288 Kconfig
and checked in rk808.c so that compilation will fail if the mainboard
Kconfig does not override it.

Originally, PMIC_BUS was only used by mainboard code as an argument
to RK808 PMIC functions. To conform to the generic RTC API, however,
the RK808 code needs to have the bus number globally defined somewhere
since the rtc_get() and rtc_set() functions don't take any args.

Since CONFIG_PMIC_BUS is globally visible, we no longer need to pass
bus number to the PMIC functions.

BUG=chrome-os-partner:34436
BRANCH=none
TEST=built and booted on Pinky

Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I73783878e507b2e7b1526dd2f81cfbdf8f1e2a55
Reviewed-on: https://chromium-review.googlesource.com/240203
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9642
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
David Hendricks 2015-01-12 13:13:30 -08:00 committed by Stefan Reinauer
parent 33df49519e
commit 4d244214ce
28 changed files with 130 additions and 98 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/veyron_brain/Kconfig
View File

@ -73,4 +73,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on CONSOLE_SERIAL_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_BRAIN

2
src/mainboard/google/veyron_brain/board.h
View File

@ -23,8 +23,6 @@
#include <boardid.h>
#include <gpio.h>
#define PMIC_BUS 0
#define GPIO_RESET GPIO(0, B, 5)
/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */

7
src/mainboard/google/veyron_brain/bootblock.c
View File

@ -50,12 +50,13 @@ void bootblock_mainboard_init(void)
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
i2c_init(PMIC_BUS, 400*KHz);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(PMIC_BUS, 1, 1200);
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(PMIC_BUS, 1, 1400);
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();

8
src/mainboard/google/veyron_brain/mainboard.c
View File

@ -63,7 +63,7 @@ static void configure_codec(void)
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
@ -77,9 +77,9 @@ static void configure_vop(void)
/* lcdc(vop) iodomain select 1.8V */
writel(RK_SETBITS(1 << 0), &rk3288_grf->io_vsel);
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(PMIC_BUS, 7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
rk808_configure_switch(1, 1); /* VCC33_LCD */
}
static void mainboard_init(device_t dev)

4
src/mainboard/google/veyron_brain/romstage.c
View File

@ -79,8 +79,8 @@ static void configure_l2ctlr(void)
static void sdmmc_power_off(void)
{
rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
rk808_configure_ldo(4, 0); /* VCCIO_SD */
rk808_configure_ldo(5, 0); /* VCC33_SD */
}
void main(void)

4
src/mainboard/google/veyron_jerry/Kconfig
View File

@ -84,4 +84,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on CONSOLE_SERIAL_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_JERRY

2
src/mainboard/google/veyron_jerry/board.h
View File

@ -23,8 +23,6 @@
#include <boardid.h>
#include <gpio.h>
#define PMIC_BUS 0
#define GPIO_RESET GPIO(0, B, 5)
/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */

7
src/mainboard/google/veyron_jerry/bootblock.c
View File

@ -48,12 +48,13 @@ void bootblock_mainboard_init(void)
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
i2c_init(PMIC_BUS, 400*KHz);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(PMIC_BUS, 1, 1200);
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(PMIC_BUS, 1, 1400);
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();

16
src/mainboard/google/veyron_jerry/mainboard.c
View File

@ -54,8 +54,8 @@ static void configure_sdmmc(void)
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
@ -77,7 +77,7 @@ static void configure_codec(void)
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
@ -93,15 +93,15 @@ static void configure_vop(void)
switch (board_id()) {
case 2:
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
}
}

4
src/mainboard/google/veyron_jerry/romstage.c
View File

@ -79,8 +79,8 @@ static void configure_l2ctlr(void)
static void sdmmc_power_off(void)
{
rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
rk808_configure_ldo(4, 0); /* VCCIO_SD */
rk808_configure_ldo(5, 0); /* VCC33_SD */
}
void main(void)

4
src/mainboard/google/veyron_mighty/Kconfig
View File

@ -84,4 +84,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on CONSOLE_SERIAL_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_MIGHTY

2
src/mainboard/google/veyron_mighty/board.h
View File

@ -23,8 +23,6 @@
#include <boardid.h>
#include <gpio.h>
#define PMIC_BUS 0
#define GPIO_RESET GPIO(0, B, 5)
/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */

7
src/mainboard/google/veyron_mighty/bootblock.c
View File

@ -48,12 +48,13 @@ void bootblock_mainboard_init(void)
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
i2c_init(PMIC_BUS, 400*KHz);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(PMIC_BUS, 1, 1200);
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(PMIC_BUS, 1, 1400);
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();

16
src/mainboard/google/veyron_mighty/mainboard.c
View File

@ -54,8 +54,8 @@ static void configure_sdmmc(void)
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
@ -77,7 +77,7 @@ static void configure_codec(void)
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
@ -93,15 +93,15 @@ static void configure_vop(void)
switch (board_id()) {
case 0:
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
}
}

4
src/mainboard/google/veyron_mighty/romstage.c
View File

@ -79,8 +79,8 @@ static void configure_l2ctlr(void)
static void sdmmc_power_off(void)
{
rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
rk808_configure_ldo(4, 0); /* VCCIO_SD */
rk808_configure_ldo(5, 0); /* VCC33_SD */
}
void main(void)

4
src/mainboard/google/veyron_pinky/Kconfig
View File

@ -84,4 +84,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on CONSOLE_SERIAL_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_PINKY

2
src/mainboard/google/veyron_pinky/board.h
View File

@ -23,8 +23,6 @@
#include <boardid.h>
#include <gpio.h>
#define PMIC_BUS 0
#define GPIO_RESET (board_id() > 0 ? GPIO(0, B, 5) : GPIO(0, B, 2))
/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */

7
src/mainboard/google/veyron_pinky/bootblock.c
View File

@ -48,12 +48,13 @@ void bootblock_mainboard_init(void)
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
i2c_init(PMIC_BUS, 400*KHz);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(PMIC_BUS, 1, 1200);
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(PMIC_BUS, 1, 1400);
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();

24
src/mainboard/google/veyron_pinky/mainboard.c
View File

@ -66,12 +66,12 @@ static void configure_sdmmc(void)
/* Note: these power rail definitions are copied in romstage.c */
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 8, 3300); /* VCCIO_SD */
rk808_configure_ldo(8, 3300); /* VCCIO_SD */
gpio_output(GPIO(7, C, 5), 1); /* SD_EN */
break;
default:
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
break;
}
@ -110,10 +110,10 @@ static void configure_codec(void)
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 5, 1800); /* VCC18_CODEC */
rk808_configure_ldo(5, 1800); /* VCC18_CODEC */
break;
default:
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
break;
}
@ -131,20 +131,20 @@ static void configure_vop(void)
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 4, 1800); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 6, 1000); /* VCC10_LCD */
rk808_configure_ldo(4, 1800); /* VCC18_LCD */
rk808_configure_ldo(6, 1000); /* VCC10_LCD */
gpio_output(GPIO(7, B, 7), 1); /* LCD_EN */
break;
case 1:
case 2:
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
break;
}

6
src/mainboard/google/veyron_pinky/romstage.c
View File

@ -81,12 +81,12 @@ static void sdmmc_power_off(void)
{
switch (board_id()) {
case 0:
rk808_configure_ldo(PMIC_BUS, 8, 0); /* VCCIO_SD */
rk808_configure_ldo(8, 0); /* VCCIO_SD */
gpio_output(GPIO(7, C, 5), 0); /* SD_EN */
break;
default:
rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
rk808_configure_ldo(4, 0); /* VCCIO_SD */
rk808_configure_ldo(5, 0); /* VCC33_SD */
break;
}
}

4
src/mainboard/google/veyron_speedy/Kconfig
View File

@ -84,4 +84,8 @@ config CONSOLE_SERIAL_UART_ADDRESS
depends on CONSOLE_SERIAL_UART
default 0xFF690000
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_SPEEDY

2
src/mainboard/google/veyron_speedy/board.h
View File

@ -23,8 +23,6 @@
#include <boardid.h>
#include <gpio.h>
#define PMIC_BUS 0
#define GPIO_RESET GPIO(0, B, 5)
/* TODO: move setup_chromeos_gpios() here once bootblock code is in mainboard */

7
src/mainboard/google/veyron_speedy/bootblock.c
View File

@ -48,12 +48,13 @@ void bootblock_mainboard_init(void)
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
i2c_init(PMIC_BUS, 400*KHz);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(PMIC_BUS, 1, 1200);
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(PMIC_BUS, 1, 1400);
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();

16
src/mainboard/google/veyron_speedy/mainboard.c
View File

@ -54,8 +54,8 @@ static void configure_sdmmc(void)
writel(RK_CLRBITS(1 << 12), &rk3288_grf->soc_con0);
/* Note: these power rail definitions are copied in romstage.c */
rk808_configure_ldo(PMIC_BUS, 4, 3300); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 3300); /* VCC33_SD */
rk808_configure_ldo(4, 3300); /* VCCIO_SD */
rk808_configure_ldo(5, 3300); /* VCC33_SD */
gpio_input(GPIO(7, A, 5)); /* SD_DET */
}
@ -77,7 +77,7 @@ static void configure_codec(void)
writel(IOMUX_I2S, &rk3288_grf->iomux_i2s);
writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk);
rk808_configure_ldo(PMIC_BUS, 6, 1800); /* VCC18_CODEC */
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel);
@ -93,15 +93,15 @@ static void configure_vop(void)
switch (board_id()) {
case 0:
rk808_configure_switch(PMIC_BUS, 2, 1); /* VCC18_LCD */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(2, 1); /* VCC18_LCD */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
default:
gpio_output(GPIO(2, B, 5), 1); /* AVDD_1V8_DISP_EN */
rk808_configure_ldo(PMIC_BUS, 7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(PMIC_BUS, 1, 1); /* VCC33_LCD */
rk808_configure_switch(1, 1); /* VCC33_LCD */
break;
}
}

4
src/mainboard/google/veyron_speedy/romstage.c
View File

@ -80,8 +80,8 @@ static void configure_l2ctlr(void)
static void sdmmc_power_off(void)
{
rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */
rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */
rk808_configure_ldo(4, 0); /* VCCIO_SD */
rk808_configure_ldo(5, 0); /* VCC33_SD */
}
void main(void)

4
src/soc/rockchip/rk3288/Kconfig
View File

@ -37,4 +37,8 @@ config BOOTBLOCK_CPU_INIT
string
default "soc/rockchip/rk3288/bootblock.c"
config PMIC_BUS
int
default -1
endif

6
src/soc/rockchip/rk3288/include/soc/rk808.h
View File

@ -20,8 +20,8 @@
#ifndef __SOC_ROCKCHIP_RK3288_PMIC_H__
#define __SOC_ROCKCHIP_RK3288_PMIC_H__
void rk808_configure_switch(uint8_t bus, int sw, int enabled);
void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts);
void rk808_configure_buck(uint8_t bus, int buck, int millivolts);
void rk808_configure_switch(int sw, int enabled);
void rk808_configure_ldo(int ldo, int millivolts);
void rk808_configure_buck(int buck, int millivolts);
#endif

51
src/soc/rockchip/rk3288/rk808.c
View File

@ -25,36 +25,49 @@
#include <stdint.h>
#include <stdlib.h>
#define RK808_ADDR 0x1b
#if CONFIG_PMIC_BUS < 0
#error "PMIC_BUS must be set in mainboard's Kconfig."
#endif
#define DCDC_EN 0x23
#define LDO_EN 0x24
#define BUCK1SEL 0x2f
#define BUCK4SEL 0x38
#define LDO_ONSEL(i) (0x39 + 2 * i)
#define LDO_SLPSEL(i) (0x3a + 2 * i)
#define RK808_ADDR 0x1b
static void rk808_clrsetbits(uint8_t bus, uint8_t reg, uint8_t clr, uint8_t set)
#define DCDC_EN 0x23
#define LDO_EN 0x24
#define BUCK1SEL 0x2f
#define BUCK4SEL 0x38
#define LDO_ONSEL(i) (0x39 + 2 * i)
#define LDO_SLPSEL(i) (0x3a + 2 * i)
static int rk808_read(uint8_t reg, uint8_t *value)
{
return i2c_readb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value);
}
static int rk808_write(uint8_t reg, uint8_t value)
{
return i2c_writeb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value);
}
static void rk808_clrsetbits(uint8_t reg, uint8_t clr, uint8_t set)
{
uint8_t value;
if (i2c_readb(bus, RK808_ADDR, reg, &value) ||
i2c_writeb(bus, RK808_ADDR, reg, (value & ~clr) | set))
if (rk808_read(reg, &value) || rk808_write(reg, (value & ~clr) | set))
printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg);
}
void rk808_configure_switch(uint8_t bus, int sw, int enabled)
void rk808_configure_switch(int sw, int enabled)
{
assert(sw == 1 || sw == 2);
rk808_clrsetbits(bus, DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4));
rk808_clrsetbits(DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4));
}
void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts)
void rk808_configure_ldo(int ldo, int millivolts)
{
uint8_t vsel;
if (!millivolts) {
rk808_clrsetbits(bus, LDO_EN, 1 << (ldo - 1), 0);
rk808_clrsetbits(LDO_EN, 1 << (ldo - 1), 0);
return;
}
@ -77,11 +90,11 @@ void rk808_configure_ldo(uint8_t bus, int ldo, int millivolts)
die("Unknown LDO index!");
}
rk808_clrsetbits(bus, LDO_ONSEL(ldo), 0x1f, vsel);
rk808_clrsetbits(bus, LDO_EN, 0, 1 << (ldo - 1));
rk808_clrsetbits(LDO_ONSEL(ldo), 0x1f, vsel);
rk808_clrsetbits(LDO_EN, 0, 1 << (ldo - 1));
}
void rk808_configure_buck(uint8_t bus, int buck, int millivolts)
void rk808_configure_buck(int buck, int millivolts)
{
uint8_t vsel;
uint8_t buck_reg;
@ -102,6 +115,6 @@ void rk808_configure_buck(uint8_t bus, int buck, int millivolts)
default:
die("fault buck index!");
}
rk808_clrsetbits(bus, buck_reg, 0x3f, vsel);
rk808_clrsetbits(bus, DCDC_EN, 0, 1 << (buck - 1));
rk808_clrsetbits(buck_reg, 0x3f, vsel);
rk808_clrsetbits(DCDC_EN, 0, 1 << (buck - 1));
}