Fix VIA EPIA-M700 target enough for a first serial boot log.
Add the respective Super I/O config in Config.lb (Winbond W83697HG), enable COM1 on the board, fix irq_table.c, as well as the PCI devices listed in Config.lb (based on lspci output). This has been tested by Jakob Bornecrantz <wallbraker@gmail.com> on hardware, i.e. there is serial output. It does not yet boot to a Linux console successfully, more fixing will be needed. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Jakob Bornecrantz <wallbraker@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
3839a8ebd8
commit
4e2ffb8812
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@ -109,21 +109,54 @@ config chip.h
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chip northbridge/via/vx800 # Northbridge
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device pci_domain 0 on
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device pci 0.0 on end # AGP Bridge
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device pci 0.0 on end # Host Bridge
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device pci 0.1 on end # Error Reporting
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device pci 0.2 on end # Host Bus Control
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device pci 0.3 on end # Memory Controller
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device pci 0.3 on end # PCI to PCI Bridge
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device pci 0.4 on end # Power Management
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device pci 0.7 on end # V-Link Controller
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device pci 0.5 on end # APIC and Central Traffic Control
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device pci 0.6 on end # Scratch Registers
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device pci 0.7 on end # North-South Module Interface Control
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device pci 1.0 on end # PCI Bridge
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# device pci f.0 on end # IDE/SATA
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device pci f.0 on end # IDE/SATA
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# device pci f.1 on end # IDE
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# device pci 10.0 on end # USB 1.1
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# device pci 10.1 on end # USB 1.1
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# device pci 10.2 on end # USB 1.1
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# device pci 10.4 on end # USB 2.0
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# device pci 11.0 on # Southbridge LPC
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# end
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device pci 10.0 on end # USB 1.1
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device pci 10.1 on end # USB 1.1
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device pci 10.2 on end # USB 1.1
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device pci 10.4 on end # USB 2.0
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device pci 11.0 on # Bus Control and Power Management (SB, LPC)
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chip superio/winbond/w83697hf
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# TODO: Check all devices, this may need some more work.
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device pnp 2e.0 off # Floppy (N/A?)
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 off # Parallel Port (N/A?)
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.6 off end # Consumer IR
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device pnp 2e.7 off end # Game port, GPIO 1
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device pnp 2e.8 off end # MIDI port, GPIO 5
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device pnp 2e.9 off end # GPIO 2-4
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HWM
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io 0x60 = 0x290
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end
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end
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end
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device pci 11.7 on end # North-South Module Interface Control
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device pci 14.0 on end # HD Audio (Azalia)
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end
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device apic_cluster 0 on # APIC cluster
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chip cpu/via/model_c7 # VIA C7
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@ -120,7 +120,7 @@ default CONFIG_UDELAY_TSC = 1
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default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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default CONFIG_HAVE_HARD_RESET = 0
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default CONFIG_HAVE_PIRQ_TABLE = 0
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default CONFIG_IRQ_SLOT_COUNT = 14
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default CONFIG_IRQ_SLOT_COUNT = 13
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default CONFIG_HAVE_ACPI_TABLES = 1
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default CONFIG_HAVE_OPTION_TABLE = 1
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default CONFIG_ROM_IMAGE_SIZE = 128 * 1024
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@ -135,6 +135,8 @@ default CONFIG_ROM_PAYLOAD = 1
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default CONFIG_CROSS_COMPILE = ""
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default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC = "gcc"
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
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default CONFIG_CBFS = 0
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##
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@ -55,6 +55,10 @@
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#include "cpu/x86/car/copy_and_run.c"
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#include "wakeup.h"
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#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
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/*
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* This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
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* http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
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@ -407,7 +411,10 @@ void amd64_main(unsigned long bist)
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* console_init()) are the same with epia-cn port.
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*/
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pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
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EmbedComInit();
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/* EmbedComInit(); */
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w83697hf_set_clksel_48(SERIAL_DEV);
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w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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/* enable_vx800_serial(); */
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/* uart_init(); */
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@ -26,23 +26,27 @@ const struct irq_routing_table intel_irq_routing_table = {
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32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
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0x00, /* Where the interrupt router lies (bus) */
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(0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */
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0xc20, /* IRQs devoted exclusively to PCI usage */
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0xca0, /* IRQs devoted exclusively to PCI usage */
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0x1106, /* Vendor */
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0x8409, /* Device */
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0x596, /* Device */
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0, /* Miniport */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0xc6, /* Checksum. 0xa0? */
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0xdb, /* Checksum. 0xa0? */
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x08 << 3) | 0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
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{0x00, (0x0b << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x0d << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x0e << 3) | 0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x0f << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x14 << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
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{0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0},
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{0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0},
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{0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0},
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{0x04, (0x04 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}}, 0x4, 0x0},
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{0x04, (0x0e << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x5, 0x0},
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{0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0},
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}
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};
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