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asrock/e350m1: Switch away from AGESA_LEGACY 

Change-Id: I335494b3339f2e5da7b1b0483b557a6eb211dfc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18710
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2016-12-20 06:43:45 +02:00
parent 3f1c5138fa
commit 4e6910c843
2 changed files with 4 additions and 79 deletions
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1
src/mainboard/asrock/e350m1/Kconfig
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@ -17,7 +17,6 @@ if BOARD_ASROCK_E350M1
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800 select SOUTHBRIDGE_AMD_CIMX_SB800

80
src/mainboard/asrock/e350m1/romstage.c
View File

@ -13,88 +13,14 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <stdint.h> #include <northbridge/amd/agesa/state_machine.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <cpu/x86/bist.h>
#include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct5572d/nct5572d.h> #include <superio/nuvoton/nct5572d/nct5572d.h>
#include <cpu/x86/lapic.h>
#include <sb_cimx.h>
#include "SBPLATFORM.h"
#include <cpu/amd/agesa/s3_resume.h>
#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void board_BeforeAgesa(struct sysinfo *cb)
{ {
u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x42);
agesawrapper_amdinitenv();
amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */
} }