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AGESA fam14 boards: Clean up devicetree 

Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30733
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-01-08 09:32:44 +02:00
parent 07cbd7684f
commit 4ebdf34e13
10 changed files with 837 additions and 843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

109
src/mainboard/amd/inagua/devicetree.cb
View File

@ -20,61 +20,60 @@ chip northbridge/amd/agesa/family14/root_complex
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge MXM lane 0
device pci 5.0 off end # PCIE P2P bridge MXM lane 1
device pci 6.0 on end # PCIE P2P bridge LAN
device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge MXM lane 0
device pci 5.0 off end # PCIE P2P bridge MXM lane 1
device pci 6.0 on end # PCIE P2P bridge LAN
device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/smsc/kbc1100
device pnp 2e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
end # kbc1100
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # OHCI FS/LS USB
device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA Express Card
device pci 15.1 on end # PCIe PortB NEC USB3.0
device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2
device pci 15.3 on end # PCIe PortD PCIE X1 SLOT
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/smsc/kbc1100
device pnp 2e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
end # kbc1100
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # OHCI FS/LS USB
device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA Express Card
device pci 15.1 on end # PCIe PortB NEC USB3.0
device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2
device pci 15.3 on end # PCIe PortD PCIE X1 SLOT
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
#device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
@ -87,6 +86,8 @@ chip northbridge/amd/agesa/family14/root_complex
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

229
src/mainboard/amd/persimmon/devicetree.cb
View File

@ -14,129 +14,129 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
#set up SB800 Fan control registers and IMC fan controls
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1"
register "fan1_enabled" = "1"
register "imc_fan_zone0_enabled" = "1"
register "imc_fan_zone1_enabled" = "1"
#set up SB800 Fan control registers and IMC fan controls
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1"
register "fan1_enabled" = "1"
register "imc_fan_zone0_enabled" = "1"
register "imc_fan_zone1_enabled" = "1"
register "fan0_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "fan1_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "fan0_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "fan1_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "imc_zone0_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone0_temp_offset" = "0x00" # No temp offset
register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
register "imc_zone0_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone0_temp_offset" = "0x00" # No temp offset
register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
register "imc_zone1_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone1_temp_offset" = "0x00" # No temp offset
register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
register "imc_zone1_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone1_temp_offset" = "0x00" # No temp offset
register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
# T56N has a Maximum operating temperature of 90C
# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
# T56N has a Maximum operating temperature of 90C
# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -152,6 +152,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

156
src/mainboard/amd/south_station/devicetree.cb
View File

@ -15,93 +15,87 @@
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 on end # PCIE P2P bridge 0x9605
device pci 6.0 on end # PCIE P2P bridge 0x9606
device pci 7.0 on end # PCIE P2P bridge 0x9607
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 on end # PCIE P2P bridge 0x9605
device pci 6.0 on end # PCIE P2P bridge 0x9606
device pci 7.0 on end # PCIE P2P bridge 0x9607
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
## chip drivers/generic/generic #dimm 0-0-0
## device i2c 50 on end
## end
## chip drivers/generic/generic #dimm 0-0-1
## device i2c 51 on end
## end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end # agesa northbridge
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #domain
end #northbridge/amd/agesa/family14/root_complex

108
src/mainboard/amd/union_station/devicetree.cb
View File

@ -15,69 +15,63 @@
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 on end # PCIE P2P bridge 0x9605
device pci 6.0 on end # PCIE P2P bridge 0x9606
device pci 7.0 on end # PCIE P2P bridge 0x9607
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 on end # PCIE P2P bridge 0x9605
device pci 6.0 on end # PCIE P2P bridge 0x9606
device pci 7.0 on end # PCIE P2P bridge 0x9607
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
## chip drivers/generic/generic #dimm 0-0-0
## device i2c 50 on end
## end
## chip drivers/generic/generic #dimm 0-0-1
## device i2c 51 on end
## end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.1 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.1 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on end # LPC 0x439d
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
register "spdAddrLookup" = "
{
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end # agesa northbridge
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #domain
end #northbridge/amd/agesa/family14/root_complex

234
src/mainboard/asrock/e350m1/devicetree.cb
View File

@ -14,129 +14,128 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge 0x9604
device pci 5.0 off end # PCIE P2P bridge 0x9605
device pci 6.0 off end # PCIE P2P bridge 0x9606
device pci 7.0 off end # PCIE P2P bridge 0x9607
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC
chip superio/nuvoton/nct5572d
device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
device pnp 2e.1 off end # LPT1; same as FDC
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
irq 0x70 = 0
end
device pnp 2e.107 off end # GPIO6
device pnp 2e.207 off end # GPIO7
device pnp 2e.307 on # GPIO8
irq 0x23 = 0x28
irq 0xe4 = 0xbf
irq 0xed = 0x27
end
device pnp 2e.407 off end # GPIO9
device pnp 2e.8 off end # WDT
device pnp 2e.009 on # GPIO2
irq 0x2a = 0x42
irq 0xe0 = 0xe3
end
device pnp 2e.109 off end # GPIO3
device pnp 2e.209 off end # GPIO4
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe7 = 0x10
end
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
io 0x62 = 0x0000 # SB-TSI currently not implemented
irq 0x70 = 5
end
device pnp 2e.c off end # PECI
device pnp 2e.d on # SUSLED
irq 0xec = 0x90
end
device pnp 2e.e off # CIRWKUP
io 0x60 = 0x0000
irq 0x70 = 0
end
device pnp 2e.f off end # GPIO_PP_OD
end
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB: NIC
device pci 15.2 on end # PCIe PortC: USB3
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
device pci 12.2 on end # USB
device pci 13.0 on end # USB
device pci 13.2 on end # USB
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC
chip superio/nuvoton/nct5572d
device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die
device pnp 2e.1 off end # LPT1; same as FDC
device pnp 2e.2 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 off # IR
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.6 off # CIR
io 0x60 = 0x100
irq 0x70 = 0
end
device pnp 2e.107 off end # GPIO6
device pnp 2e.207 off end # GPIO7
device pnp 2e.307 on # GPIO8
irq 0x23 = 0x28
irq 0xe4 = 0xbf
irq 0xed = 0x27
end
device pnp 2e.407 off end # GPIO9
device pnp 2e.8 off end # WDT
device pnp 2e.009 on # GPIO2
irq 0x2a = 0x42
irq 0xe0 = 0xe3
end
device pnp 2e.109 off end # GPIO3
device pnp 2e.209 off end # GPIO4
device pnp 2e.309 off end # GPIO5
device pnp 2e.a on # ACPI
irq 0xe7 = 0x10
end
device pnp 2e.b on # HW Monitor
io 0x60 = 0x290
io 0x62 = 0x0000 # SB-TSI currently not implemented
irq 0x70 = 5
end
device pnp 2e.c off end # PECI
device pnp 2e.d on # SUSLED
irq 0xec = 0x90
end
device pnp 2e.e off # CIRWKUP
io 0x60 = 0x0000
irq 0x70 = 0
end
device pnp 2e.f off end # GPIO_PP_OD
end
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB: NIC
device pci 15.2 on end # PCIe PortC: USB3
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB3
device pci 16.2 off end # EHCI USB3
# gpp_configuration options
#0000: PortA lanes[3:0]
#0001: N/A
#0010: PortA lanes[1:0], PortB lanes[3:2]
#0011: PortA lanes[1:0], PortB lane2, PortC lane3
#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
register "gpp_configuration" = "4"
# gpp_configuration options
#0000: PortA lanes[3:0]
#0001: N/A
#0010: PortA lanes[1:0], PortB lanes[3:2]
#0011: PortA lanes[1:0], PortB lane2, PortC lane3
#0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3.
register "gpp_configuration" = "4"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
#
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
register "spdAddrLookup" = "
{
@ -144,6 +143,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

222
src/mainboard/elmex/pcm205400/devicetree.cb
View File

@ -14,125 +14,126 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge PCIe slot
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 off end # Keyboard
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 on end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f81865f
device pnp 4e.0 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 off end # Hardware Monitor
device pnp 4e.5 off end # Keyboard
device pnp 4e.6 off end # GPIO
device pnp 4e.a off end # PME
device pnp 4e.10 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.11 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end # f81865f
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
#set up SB800 Fan control registers and IMC fan controls
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1"
register "fan1_enabled" = "1"
register "imc_fan_zone0_enabled" = "1"
register "imc_fan_zone1_enabled" = "1"
register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
register "fan0_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "fan1_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
#set up SB800 Fan control registers and IMC fan controls
register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common
register "fan0_enabled" = "1"
register "fan1_enabled" = "1"
register "imc_fan_zone0_enabled" = "1"
register "imc_fan_zone1_enabled" = "1"
register "imc_zone0_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone0_temp_offset" = "0x00" # No temp offset
register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
register "fan0_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "fan1_config_vals" = "{ \
FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \
FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }"
register "imc_zone1_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone1_temp_offset" = "0x00" # No temp offset
register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
register "imc_zone0_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0"
register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone0_temp_offset" = "0x00" # No temp offset
register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping
# T56N has a Maximum operating temperature of 90C
# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
register "imc_zone1_mode1" = " \
IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \
IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1"
register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \
IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED"
register "imc_zone1_temp_offset" = "0x00" # No temp offset
register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis
register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address
register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number
register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate
register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
# T56N has a Maximum operating temperature of 90C
# ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C
# ZONEX_FANSPEEDS - Fan speeds as a "percentage"
register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }"
register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }"
register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }"
register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }"
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -148,6 +149,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

194
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
View File

@ -15,114 +15,113 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
# device pci 1.1 on end # Internal Audio P2P bridge 0x1314
device pci 4.0 on end # PCIE P2P bridge PCIe slot
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge PCIe slot
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f71869ad
register "multi_function_register_1" = "0x01"
register "multi_function_register_2" = "0x6f"
register "multi_function_register_3" = "0x24"
register "multi_function_register_4" = "0x00"
register "multi_function_register_5" = "0x60"
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f71869ad
register "multi_function_register_1" = "0x01"
register "multi_function_register_2" = "0x6f"
register "multi_function_register_3" = "0x24"
register "multi_function_register_4" = "0x00"
register "multi_function_register_5" = "0x60"
# HWM configuration registers
register "hwm_smbus_address" = "0x98"
register "hwm_smbus_control_reg" = "0x02"
register "hwm_fan_type_sel_reg" = "0x00"
register "hwm_fan1_temp_adj_rate_reg" = "0x33"
register "hwm_fan_mode_sel_reg" = "0x07"
register "hwm_fan1_idx_rpm_mode" = "0x0e"
register "hwm_fan1_seg1_speed_count" = "0xff"
register "hwm_fan1_seg2_speed_count" = "0x0e"
register "hwm_fan1_seg3_speed_count" = "0x07"
register "hwm_fan1_temp_map_sel" = "0x8c"
register "hwm_temp_sensor_type" = "0x0E" # default value
register "hwm_smbus_address" = "0x98"
register "hwm_smbus_control_reg" = "0x02"
register "hwm_fan_type_sel_reg" = "0x00"
register "hwm_fan1_temp_adj_rate_reg" = "0x33"
register "hwm_fan_mode_sel_reg" = "0x07"
register "hwm_fan1_idx_rpm_mode" = "0x0e"
register "hwm_fan1_seg1_speed_count" = "0xff"
register "hwm_fan1_seg2_speed_count" = "0x0e"
register "hwm_fan1_seg3_speed_count" = "0x07"
register "hwm_fan1_temp_map_sel" = "0x8c"
register "hwm_temp_sensor_type" = "0x0E" # default value
#
# XXX: 4e is the default index port and .xy is the
# LDN indexing the pnp_info array found in the superio.c
# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
# see page 18 from Fintek F71869 V1.1 datasheet.
device pnp 2e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.00 off # Floppy
io 0x60 = 0x3f0
irq 0x70 = 6
drq 0x74 = 2
end
device pnp 2e.01 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
# COM2 not physically wired on board.
device pnp 2e.02 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.03 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.04 on # Hardware Monitor
io 0x60 = 0x225 # Fintek datasheet says 0x295.
irq 0x70 = 0
end
device pnp 2e.05 on # KBC
io 0x60 = 0x060
irq 0x70 = 1 # Keyboard IRQ
irq 0x72 = 12 # Mouse IRQ
end
device pnp 2e.06 off end # GPIO
device pnp 2e.07 on end # WDT
device pnp 2e.08 off end # CIR
device pnp 2e.0a on end # PME
end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 on end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13 (0x4397)
device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes.
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
device pnp 2e.02 off # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.03 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 3
end
device pnp 2e.04 on # Hardware Monitor
io 0x60 = 0x225 # Fintek datasheet says 0x295.
irq 0x70 = 0
end
device pnp 2e.05 on # KBC
io 0x60 = 0x060
irq 0x70 = 1 # Keyboard IRQ
irq 0x72 = 12 # Mouse IRQ
end
device pnp 2e.06 off end # GPIO
device pnp 2e.07 on end # WDT
device pnp 2e.08 off end # CIR
device pnp 2e.0a on end # PME
end # f71869ad
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # OHCI FS/LS USB (0x4399)
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168)
device pci 15.1 on end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13 (0x4397)
device pci 16.2 on end # EHCI USB 10-13 (0x4396)
register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes.
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -143,6 +142,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

141
src/mainboard/lippert/frontrunner-af/devicetree.cb
View File

@ -14,78 +14,80 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 off end # PCIE P2P bridge
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC
device pci 5.0 off end # PCIE P2P bridge
device pci 6.0 off end # PCIE P2P bridge
device pci 7.0 off end # PCIE P2P bridge
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 off end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/smsc/smscsuperio
device pnp 4e.0 off end # Floppy
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 4e.A on # Runtime Regs
io 0x60 = 0x0E00
drq 0xF0 = 0x0B # no 32kHz
end
end # smscsuperio
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 off end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/smsc/smscsuperio
device pnp 4e.0 off end # Floppy
device pnp 4e.3 off end # Parallel Port
device pnp 4e.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 4e.A on # Runtime Regs
io 0x60 = 0x0E00
drq 0xF0 = 0x0B # no 32kHz
end
end # smscsuperio
end #LPC
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -101,6 +103,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end # agesa northbridge
end #domain
end #northbridge/amd/agesa/family14/root_complex

150
src/mainboard/lippert/toucan-af/devicetree.cb
View File

@ -14,84 +14,84 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
#device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge
device pci 5.0 on end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge
device pci 7.0 on end # PCIE P2P bridge on-board NIC
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
#device pci 1.1 on end # Internal HDMI Audio
device pci 4.0 on end # PCIE P2P bridge
device pci 5.0 on end # PCIE P2P bridge
device pci 6.0 on end # PCIE P2P bridge
device pci 7.0 on end # PCIE P2P bridge on-board NIC
device pci 8.0 off end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 off end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/winbond/w83627dhg
device pnp 4e.0 off end # Floppy
device pnp 4e.1 off end # Parallel Port
device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.5 on # Keyboard, Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
#device pnp 4e.6 off end # SPI
device pnp 4e.307 off end # GPIO6
device pnp 4e.8 off end # WDTO, PLED
device pnp 4e.009 off end # GPIO2
device pnp 4e.109 off end # GPIO3
device pnp 4e.209 off end # GPIO4
device pnp 4e.309 off end # GPIO5
device pnp 4e.A off end # ACPI
device pnp 4e.B off end # HW Monitor
end # w83627dhg
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB
device pci 15.2 on end # PCIe PortC
device pci 15.3 on end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on # SM
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
chip drivers/generic/generic #dimm 0-0-1
device i2c 51 off end
end
end # SM
device pci 14.1 off end # IDE 0x439c
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/winbond/w83627dhg
device pnp 4e.0 off end # Floppy
device pnp 4e.1 off end # Parallel Port
device pnp 4e.2 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 4e.3 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 4e.5 on # Keyboard, Mouse
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
#device pnp 4e.6 off end # SPI
device pnp 4e.307 off end # GPIO6
device pnp 4e.8 off end # WDTO, PLED
device pnp 4e.009 off end # GPIO2
device pnp 4e.109 off end # GPIO3
device pnp 4e.209 off end # GPIO4
device pnp 4e.309 off end # GPIO5
device pnp 4e.A off end # ACPI
device pnp 4e.B off end # HW Monitor
end # w83627dhg
end #LPC
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 off end # OHCI FS/LS USB
device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB
device pci 15.2 on end # PCIe PortC
device pci 15.3 on end # PCIe PortD
device pci 16.0 off end # OHCI USB 10-13
device pci 16.2 off end # EHCI USB 10-13
register "gpp_configuration" = "4" #1:1:1:1
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -106,7 +106,7 @@ chip northbridge/amd/agesa/family14/root_complex
{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
}"
end # agesa northbridge
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #domain
end #northbridge/amd/agesa/family14/root_complex

137
src/mainboard/pcengines/apu1/devicetree.cb
View File

@ -15,79 +15,78 @@
#
chip northbridge/amd/agesa/family14/root_complex
device cpu_cluster 0 on
chip cpu/amd/agesa/family14
device lapic 0 on end
end
chip cpu/amd/agesa/family14
device lapic 0 on end
end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
chip northbridge/amd/agesa/family14 # CPU side of HT root complex
# device pci 18.0 on # northbridge
chip northbridge/amd/agesa/family14 # PCI side of HT root complex
device pci 0.0 on end # Root Complex
device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC 3
device pci 5.0 on end # PCIE P2P bridge on-board NIC 2
device pci 6.0 on end # PCIE P2P bridge on-board NIC 1
device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip northbridge/amd/agesa/family14
device pci 0.0 on end # Root Complex
device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456]
device pci 4.0 on end # PCIE P2P bridge on-board NIC 3
device pci 5.0 on end # PCIE P2P bridge on-board NIC 2
device pci 6.0 on end # PCIE P2P bridge on-board NIC 1
device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1
device pci 8.0 on end # NB/SB Link P2P bridge
end # agesa northbridge
chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on end # SMBus
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.3 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.10 off
# UART C is conditionally turned on
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 2e.11 off
# UART D is conditionally turned on
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 off end
device pnp 2e.107 off end
device pnp 2e.607 off end
device pnp 2e.e off end
chip southbridge/amd/cimx/sb800
device pci 11.0 on end # SATA
device pci 12.0 on end # OHCI USB 0-4
device pci 12.2 on end # EHCI USB 0-4
device pci 13.0 on end # OHCI USB 5-9
device pci 13.2 on end # EHCI USB 5-9
device pci 14.0 on end # SMBus
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
device pnp 2e.2 on
io 0x60 = 0x3f8
irq 0x70 = 4
end
end #LPC
device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
device pci 14.5 off end # OHCI FS/LS USB
#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA miniPCIe slot 2
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "disconnect_pcib" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
# end # device pci 18.0
# These seem unnecessary
device pnp 2e.3 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.10 off
# UART C is conditionally turned on
io 0x60 = 0x3e8
irq 0x70 = 4
end
device pnp 2e.11 off
# UART D is conditionally turned on
io 0x60 = 0x2e8
irq 0x70 = 3
end
device pnp 2e.8 off end
device pnp 2e.f off end
# GPIO0 and GPIO1 are conditionally turned on
device pnp 2e.007 off end
device pnp 2e.107 off end
device pnp 2e.607 off end
device pnp 2e.e off end
end
end #LPC
device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
device pci 14.5 off end # OHCI FS/LS USB
#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
device pci 15.0 on end # PCIe PortA miniPCIe slot 2
device pci 15.1 off end # PCIe PortB
device pci 15.2 off end # PCIe PortC
device pci 15.3 off end # PCIe PortD
device pci 16.0 on end # OHCI USB 10-13
device pci 16.2 on end # EHCI USB 10-13
register "gpp_configuration" = "4" # GPP_CFGMODE_X1111
register "disconnect_pcib" = "1"
register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
end #southbridge/amd/cimx/sb800
chip northbridge/amd/agesa/family14
# These seem unnecessary
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
@ -96,7 +95,7 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
end # agesa northbridge
end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
end #domain
end #northbridge/amd/agesa/family14/root_complex