soc/intel/meteorlake: Move P2SB PCI resource into P2SB device

This patch ensures the P2SB PCI device resource is getting reserved
so that the resource allocator is not assigning this resource to any
other PCI device during the PCI enumeration.

BUG=b:254207628
TEST=Able to ensure on the Google/Rex device, the PCI enumeration
is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3.
Instead the 0xE000_0000 address is being assigned to the P2SB
PCI device.

Without this patch:
[SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align
            20 gran 20 limit ec1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e0000000 size c200000 align 12 gran
             12 limit ec1fffff flags 40000200 index 10

With this patch:
[SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align
            20 gran 20 limit ed1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e1000000 size c200000 align 12 gran
             12 limit ed1fffff flags 40000200 index 10
......
[DEBUG]     PCI: 00:1f.1
[SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align
            0 gran 0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

src/soc/intel/meteorlake/chip.c

@@ -182,6 +182,9 @@ static void soc_enable(struct device *dev)
 	else if (dev->path.type == DEVICE_PATH_PCI &&
 		 dev->path.pci.devfn == PCI_DEVFN_PMC)
 		dev->ops = &pmc_ops;
+	else if (dev->path.type == DEVICE_PATH_PCI &&
+		 dev->path.pci.devfn == PCI_DEVFN_P2SB)
+		dev->ops = &soc_p2sb_ops;
 	else if (dev->path.type == DEVICE_PATH_PCI &&
 		 dev->path.pci.devfn == PCI_DEVFN_IOE_P2SB)
 		dev->ops = &ioe_p2sb_ops;

src/soc/intel/meteorlake/chipset.cb

@@ -164,7 +164,7 @@ chip soc/intel/meteorlake
 		device pci 1e.4 alias tsn_gbe1 off end
 		device pci 1e.5 alias tsn_gbe2 off end
 		device pci 1f.0 alias soc_espi on end
-		device pci 1f.1 alias p2sb off end
+		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
 		device pci 1f.4 alias smbus off end

src/soc/intel/meteorlake/include/soc/p2sb.h

@@ -9,5 +9,6 @@
 #define PCH_P2SB_EPMASK0		0x220
 
 extern struct device_operations ioe_p2sb_ops;
+extern struct device_operations soc_p2sb_ops;
 
 #endif

src/soc/intel/meteorlake/p2sb.c

@@ -2,6 +2,7 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci_def.h>
 #include <intelblocks/p2sb.h>
 #include <soc/iomap.h>
 
@@ -37,8 +38,25 @@ static void ioe_p2sb_read_resources(struct device *dev)
 	mmio_resource_kb(dev, 0, IOM_BASE_ADDR / KiB, IOM_BASE_SIZE / KiB);
 }
 
+static void p2sb_read_resources(struct device *dev)
+{
+	/*
+	 * There's only one resource on the P2SB device. It's also already
+	 * manually set to a fixed address in earlier boot stages.
+	 * The following code makes sure that it doesn't change even the
+	 * resource allocator is being run.
+	 */
+	mmio_range(dev, PCI_BASE_ADDRESS_0, P2SB_BAR, P2SB_SIZE);
+}
+
 struct device_operations ioe_p2sb_ops = {
 	.read_resources   = ioe_p2sb_read_resources,
 	.set_resources    = noop_set_resources,
 	.scan_bus         = scan_static_bus,
 };
+
+struct device_operations soc_p2sb_ops = {
+	.read_resources   = p2sb_read_resources,
+	.set_resources    = noop_set_resources,
+	.scan_bus         = scan_static_bus,
+};