broadwell: Change all SoC headers to <soc/headername.h> system

This patch aligns broadwell to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.

Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/mainboard/google/samus/acpi_tables.c

@@ -29,8 +29,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
 #include "thermal.h"
 
 void acpi_create_gnvs(global_nvs_t *gnvs)

src/mainboard/google/samus/chromeos.c

@@ -26,7 +26,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 
 /* SPI Write protect is GPIO 16 */

src/mainboard/google/samus/fadt.c

@@ -19,7 +19,7 @@
  */
 
 #include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/google/samus/gpio.h

@@ -20,7 +20,7 @@
 #ifndef SAMUS_GPIO_H
 #define SAMUS_GPIO_H
 
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 #define SAMUS_GPIO_PP3300_AUTOBAHN_EN	23
 #define SAMUS_GPIO_SSD_RESET_L		47

src/mainboard/google/samus/pei_data.c

@@ -19,9 +19,9 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {

src/mainboard/google/samus/romstage.c

@@ -22,12 +22,12 @@
 #include <console/console.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
-#include <broadwell/cpu.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/pm.h>
-#include <broadwell/romstage.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
 #include <mainboard/google/samus/spd/spd.h>
 #include <mainboard/google/samus/gpio.h>
 

src/mainboard/google/samus/smihandler.c

@@ -21,15 +21,15 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include <elog.h>
 #include <ec/google/chromeec/ec.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iomap.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include "ec.h"
 #include "gpio.h"
 

src/mainboard/google/samus/spd/spd.c

@@ -21,9 +21,9 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/samus/ec.h>
 #include <mainboard/google/samus/gpio.h>

src/mainboard/intel/wtm2/acpi_tables.c

@@ -29,8 +29,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
 #include "thermal.h"
 
 void acpi_create_gnvs(global_nvs_t *gnvs)

src/mainboard/intel/wtm2/chromeos.c

@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 /* Compile-time settings for developer and recovery mode. */
 #define DEV_MODE_SETTING 1

src/mainboard/intel/wtm2/fadt.c

@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/intel/wtm2/gpio.h

@@ -20,7 +20,7 @@
 #ifndef INTEL_WTM2_GPIO_H
 #define INTEL_WTM2_GPIO_H
 
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 static const struct gpio_config mainboard_gpio_config[] = {
 	PCH_GPIO_NATIVE,        /* 0: LPSS_UART1_RXD */

src/mainboard/intel/wtm2/mainboard_smi.c

@@ -20,8 +20,8 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <broadwell/nvs.h>
-#include <broadwell/smm.h>
+#include <soc/nvs.h>
+#include <soc/smm.h>
 
 int mainboard_io_trap_handler(int smif)
 {

src/mainboard/intel/wtm2/pei_data.c

@@ -20,9 +20,9 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {

src/mainboard/intel/wtm2/romstage.c

@@ -21,10 +21,10 @@
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
 #include "gpio.h"
 
 void mainboard_romstage_entry(struct romstage_params *rp)

src/soc/intel/broadwell/Makefile.inc

@@ -70,7 +70,7 @@ romstage-y += usbdebug.c
 smm-y      += usbdebug.c
 endif
 
-CPPFLAGS_common += -Isrc/soc/intel/broadwell/
+CPPFLAGS_common += -Isrc/soc/intel/broadwell/include
 
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware

src/soc/intel/broadwell/acpi.c

@@ -34,14 +34,14 @@
 #include <cpu/intel/turbo.h>
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>
-#include <broadwell/acpi.h>
-#include <broadwell/cpu.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <chip.h>
+#include <soc/acpi.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/intel/broadwell/chip.h>
 
 /*
  * List of supported C-states in this processor. Only the ULT parts support C8,

src/soc/intel/broadwell/acpi/pch.asl

@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <soc/intel/broadwell/broadwell/iomap.h>
+#include <soc/iomap.h>
 
 Scope (\)
 {

src/soc/intel/broadwell/acpi/systemagent.asl

@@ -18,7 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <soc/intel/broadwell/broadwell/iomap.h>
+#include <soc/iomap.h>
 
 Name (_HID, EISAID ("PNP0A08"))	// PCIe
 Name (_CID, EISAID ("PNP0A03"))	// PCI

src/soc/intel/broadwell/adsp.c

@@ -25,14 +25,14 @@
 #include <device/pci_ops.h>
 #include <arch/io.h>
 #include <delay.h>
-#include <broadwell/adsp.h>
-#include <broadwell/device_nvs.h>
-#include <broadwell/iobp.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/adsp.h>
+#include <soc/device_nvs.h>
+#include <soc/iobp.h>
+#include <soc/nvs.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
 
 static void adsp_init(struct device *dev)
 {

src/soc/intel/broadwell/bootblock/cpu.c

@@ -25,8 +25,8 @@
 #include <arch/io.h>
 #include <halt.h>
 #include <cpu/intel/microcode/microcode.c>
-#include <broadwell/rcba.h>
-#include <broadwell/msr.h>
+#include <soc/rcba.h>
+#include <soc/msr.h>
 
 static void set_var_mtrr(
 	unsigned reg, unsigned base, unsigned size, unsigned type)

src/soc/intel/broadwell/bootblock/pch.c

@@ -19,11 +19,11 @@
 
 #include <arch/io.h>
 #include <cpu/x86/tsc.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/rcba.h>
-#include <broadwell/spi.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
 
 static void store_initial_timestamp(void)
 {

src/soc/intel/broadwell/bootblock/systemagent.c

@@ -18,8 +18,8 @@
  */
 
 #include <arch/io.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
 
 static void bootblock_northbridge_init(void)
 {

src/soc/intel/broadwell/chip.c

@@ -20,9 +20,9 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <chip.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
 
 static void pci_domain_set_resources(device_t dev)
 {

src/soc/intel/broadwell/cpu.c

@@ -36,14 +36,14 @@
 #include <cpu/x86/smm.h>
 #include <delay.h>
 #include <pc80/mc146818rtc.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
-#include <chip.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
+#include <soc/intel/broadwell/chip.h>
 
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {

src/soc/intel/broadwell/cpu_info.c

@@ -21,9 +21,9 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/systemagent.h>
 
 u32 cpu_family_model(void)
 {

src/soc/intel/broadwell/ehci.c

@@ -24,8 +24,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
-#include <broadwell/ehci.h>
-#include <broadwell/pch.h>
+#include <soc/ehci.h>
+#include <soc/pch.h>
 
 static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {

src/soc/intel/broadwell/elog.c

@@ -22,8 +22,8 @@
 #include <console/console.h>
 #include <stdint.h>
 #include <elog.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pm.h>
+#include <soc/lpc.h>
+#include <soc/pm.h>
 
 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
 {

src/soc/intel/broadwell/finalize.c

@@ -25,12 +25,12 @@
 #include <reg_script.h>
 #include <spi-generic.h>
 #include <stdlib.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/lpc.h>
-#include <broadwell/me.h>
-#include <broadwell/rcba.h>
-#include <broadwell/spi.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/lpc.h>
+#include <soc/me.h>
+#include <soc/rcba.h>
+#include <soc/spi.h>
+#include <soc/systemagent.h>
 
 const struct reg_script system_agent_finalize_script[] = {
 	REG_PCI_OR16(0x50, 1 << 0),				/* GGC */

src/soc/intel/broadwell/gpio.c

@@ -22,9 +22,9 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/pm.h>
 
 /*
  * This function will return a number that indicates which PIRQ

src/soc/intel/broadwell/hda.c

@@ -27,9 +27,9 @@
 #include <arch/io.h>
 #include <delay.h>
 #include <soc/intel/common/hda_verb.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
 
 const u32 * cim_verb_data = NULL;
 u32 cim_verb_data_size = 0;

src/soc/intel/broadwell/igd.c

@@ -28,10 +28,10 @@
 #include <string.h>
 #include <reg_script.h>
 #include <drivers/intel/gma/i915_reg.h>
-#include <broadwell/cpu.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/systemagent.h>
-#include <chip.h>
+#include <soc/cpu.h>
+#include <soc/ramstage.h>
+#include <soc/systemagent.h>
+#include <soc/intel/broadwell/chip.h>
 
 #define GT_RETRY 		1000
 #define GT_CDCLK_337		0

src/soc/intel/broadwell/include/soc/acpi.h

@@ -21,7 +21,7 @@
 #define _BROADWELL_ACPI_H_
 
 #include <arch/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/nvs.h>
 
 /* P-state configuration */
 #define PSS_MAX_ENTRIES			8

src/soc/intel/broadwell/include/soc/nvs.h

@@ -22,7 +22,7 @@
 #define _BROADWELL_NVS_H_
 
 #include <vendorcode/google/chromeos/gnvs.h>
-#include <broadwell/device_nvs.h>
+#include <soc/device_nvs.h>
 
 typedef struct {
 	/* Miscellaneous */

src/soc/intel/broadwell/include/soc/pei_wrapper.h

@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_PEI_WRAPPER_H_
 #define _BROADWELL_PEI_WRAPPER_H_
 
-#include <broadwell/pei_data.h>
+#include <soc/pei_data.h>
 
 typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
 

src/soc/intel/broadwell/include/soc/ramstage.h

@@ -21,7 +21,7 @@
 #define _BROADWELL_RAMSTAGE_H_
 
 #include <device/device.h>
-#include <chip.h>
+#include <soc/intel/broadwell/chip.h>
 
 void broadwell_init_pre_device(void *chip_info);
 void broadwell_init_cpus(device_t dev);

src/soc/intel/broadwell/include/soc/rcba.h

@@ -20,7 +20,7 @@
 #ifndef _BROADWELL_RCBA_H_
 #define _BROADWELL_RCBA_H_
 
-#include <broadwell/iomap.h>
+#include <soc/iomap.h>
 
 #define RCBA8(x)	*((volatile u8 *)(RCBA_BASE_ADDRESS + x))
 #define RCBA16(x)	*((volatile u16 *)(RCBA_BASE_ADDRESS + x))

src/soc/intel/broadwell/include/soc/systemagent.h

@@ -21,7 +21,7 @@
 #ifndef _BROADWELL_SYSTEMAGENT_H_
 #define _BROADWELL_SYSTEMAGENT_H_
 
-#include <broadwell/iomap.h>
+#include <soc/iomap.h>
 
 #define SA_IGD_OPROM_VENDEV	0x80860406
 

src/soc/intel/broadwell/iobp.c

@@ -20,8 +20,8 @@
 #include <console/console.h>
 #include <delay.h>
 #include <arch/io.h>
-#include <broadwell/iobp.h>
-#include <broadwell/rcba.h>
+#include <soc/iobp.h>
+#include <soc/rcba.h>
 
 #define IOBP_RETRY 1000
 

src/soc/intel/broadwell/lpc.c

@@ -34,17 +34,17 @@
 #include <cbmem.h>
 #include <reg_script.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iobp.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/iobp.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <cpu/cpu.h>

src/soc/intel/broadwell/me.c

@@ -35,13 +35,13 @@
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
-#include <broadwell/me.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
+#include <soc/me.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
 
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>

src/soc/intel/broadwell/me_status.c

@@ -23,8 +23,8 @@
 #include <device/pci_ids.h>
 #include <stdlib.h>
 #include <string.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/me.h>
+#include <soc/pci_devs.h>
+#include <soc/me.h>
 #include <delay.h>
 
 static inline void me_read_dword_ptr(void *ptr, int offset)

src/soc/intel/broadwell/memmap.c

@@ -20,8 +20,8 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <device/pci.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/systemagent.h>
+#include <soc/pci_devs.h>
+#include <soc/systemagent.h>
 
 static uintptr_t dpr_region_start(void)
 {

src/soc/intel/broadwell/minihd.c

@@ -28,7 +28,7 @@
 #include <delay.h>
 #include <stdlib.h>
 #include <soc/intel/common/hda_verb.h>
-#include <broadwell/ramstage.h>
+#include <soc/ramstage.h>
 
 static const u32 minihd_verb_table[] = {
 	/* coreboot specific header */

src/soc/intel/broadwell/monotonic_timer.c

@@ -20,7 +20,7 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <timer.h>
-#include <broadwell/msr.h>
+#include <soc/msr.h>
 
 static struct monotonic_counter {
 	int initialized;

src/soc/intel/broadwell/pch.c

@@ -24,13 +24,13 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
-#include <broadwell/iobp.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/serialio.h>
-#include <broadwell/spi.h>
+#include <soc/iobp.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/serialio.h>
+#include <soc/spi.h>
 
 u8 pch_revision(void)
 {

src/soc/intel/broadwell/pcie.c

@@ -24,14 +24,14 @@
 #include <device/pciexp.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#include <broadwell/gpio.h>
-#include <broadwell/lpc.h>
-#include <broadwell/iobp.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/rcba.h>
-#include <chip.h>
-#include <broadwell/cpu.h>
+#include <soc/gpio.h>
+#include <soc/lpc.h>
+#include <soc/iobp.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/rcba.h>
+#include <soc/intel/broadwell/chip.h>
+#include <soc/cpu.h>
 
 static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
 static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);

src/soc/intel/broadwell/pei_data.c

@@ -20,10 +20,10 @@
 #include <stdlib.h>
 #include <stdint.h>
 #include <console/streams.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/smm.h>
+#include <soc/iomap.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/smm.h>
 
 static void ABI_X86 send_to_console(unsigned char b)
 {

src/soc/intel/broadwell/pmutil.c

@@ -27,11 +27,11 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/gpio.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/gpio.h>
 
 /* Print status bits with descriptive names */
 static void print_status_bits(u32 status, const char *bit_names[])

src/soc/intel/broadwell/ramstage.c

@@ -23,10 +23,10 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <string.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pm.h>
-#include <broadwell/ramstage.h>
-#include <chip.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/ramstage.h>
+#include <soc/intel/broadwell/chip.h>
 
 /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
 static void s3_save_acpi_wake_source(global_nvs_t *gnvs)

src/soc/intel/broadwell/refcode.c

@@ -30,9 +30,9 @@
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/vboot_handoff.h>
 #endif
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/ramstage.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/ramstage.h>
 
 static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
 {

src/soc/intel/broadwell/reset.c

@@ -21,7 +21,7 @@
 #include <arch/io.h>
 #include <halt.h>
 #include <reset.h>
-#include <broadwell/reset.h>
+#include <soc/reset.h>
 
 /*
  * Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92

src/soc/intel/broadwell/romstage/cpu.c

@@ -21,9 +21,9 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/romstage.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/romstage.h>
 
 u32 cpu_family_model(void)
 {

src/soc/intel/broadwell/romstage/pch.c

@@ -22,15 +22,15 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/rcba.h>
-#include <broadwell/romstage.h>
-#include <broadwell/smbus.h>
-#include <chip.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
+#include <soc/smbus.h>
+#include <soc/intel/broadwell/chip.h>
 
 const struct reg_script pch_early_init_script[] = {
 	/* Setup southbridge BARs */

src/soc/intel/broadwell/romstage/power_state.c

@@ -28,11 +28,11 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
-#include <broadwell/iomap.h>
-#include <broadwell/lpc.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/romstage.h>
+#include <soc/iomap.h>
+#include <soc/lpc.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
 
 static struct chipset_power_state power_state CAR_GLOBAL;
 

src/soc/intel/broadwell/romstage/raminit.c

@@ -31,14 +31,14 @@
 #endif
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/intel/common/mrc_cache.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/pm.h>
-#include <broadwell/reset.h>
-#include <broadwell/romstage.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
 
 /*
  * Find PEI executable in coreboot filesystem and execute it.

src/soc/intel/broadwell/romstage/report_platform.c

@@ -23,11 +23,11 @@
 #include <device/pci.h>
 #include <string.h>
 #include <cpu/x86/msr.h>
-#include <broadwell/cpu.h>
-#include <broadwell/pch.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/romstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
 
 static struct {
 	u32 cpuid;

src/soc/intel/broadwell/romstage/romstage.c

@@ -31,12 +31,12 @@
 #include <ramstage_cache.h>
 #include <romstage_handoff.h>
 #include <timestamp.h>
-#include <broadwell/me.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pm.h>
-#include <broadwell/reset.h>
-#include <broadwell/romstage.h>
-#include <broadwell/spi.h>
+#include <soc/me.h>
+#include <soc/pei_data.h>
+#include <soc/pm.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <soc/spi.h>
 
 /* Entry from cache-as-ram.inc. */
 void * asmlinkage romstage_main(unsigned long bist,

src/soc/intel/broadwell/romstage/smbus.c

@@ -23,10 +23,10 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/smbus.h>
-#include <broadwell/romstage.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/smbus.h>
+#include <soc/romstage.h>
 
 static const struct reg_script smbus_init_script[] = {
 	/* Set SMBUS I/O base address */

src/soc/intel/broadwell/romstage/spi.c

@@ -22,9 +22,9 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <delay.h>
-#include <broadwell/spi.h>
-#include <broadwell/rcba.h>
-#include <broadwell/romstage.h>
+#include <soc/spi.h>
+#include <soc/rcba.h>
+#include <soc/romstage.h>
 
 #define SPI_DELAY 10     /* 10us */
 #define SPI_RETRY 200000 /* 2s */

src/soc/intel/broadwell/romstage/stack.c

@@ -24,7 +24,7 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
-#include <broadwell/romstage.h>
+#include <soc/romstage.h>
 
 static inline uint32_t *stack_push(u32 *stack, u32 value)
 {

src/soc/intel/broadwell/romstage/systemagent.c

@@ -22,10 +22,10 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <reg_script.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/romstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+#include <soc/systemagent.h>
 
 static const struct reg_script systemagent_early_init_script[] = {
 	REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1),

src/soc/intel/broadwell/romstage/uart.c

@@ -24,8 +24,8 @@
 #include <reg_script.h>
 #include <stdint.h>
 #include <uart8250.h>
-#include <broadwell/iobp.h>
-#include <broadwell/serialio.h>
+#include <soc/iobp.h>
+#include <soc/serialio.h>
 
 const struct reg_script uart_init[] = {
 	/* Set MMIO BAR */

src/soc/intel/broadwell/sata.c

@@ -24,11 +24,11 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <delay.h>
-#include <broadwell/iobp.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/sata.h>
-#include <chip.h>
+#include <soc/iobp.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/sata.h>
+#include <soc/intel/broadwell/chip.h>
 
 static inline u32 sir_read(struct device *dev, int idx)
 {

src/soc/intel/broadwell/serialio.c

@@ -25,14 +25,14 @@
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
 #include <stdlib.h>
-#include <broadwell/iobp.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pch.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/rcba.h>
-#include <broadwell/serialio.h>
-#include <chip.h>
+#include <soc/iobp.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pch.h>
+#include <soc/ramstage.h>
+#include <soc/rcba.h>
+#include <soc/serialio.h>
+#include <soc/intel/broadwell/chip.h>
 
 /* Set D3Hot Power State in ACPI mode */
 static void serialio_enable_d3hot(struct resource *res)

src/soc/intel/broadwell/smbus.c

@@ -27,9 +27,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <broadwell/iomap.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/smbus.h>
+#include <soc/iomap.h>
+#include <soc/ramstage.h>
+#include <soc/smbus.h>
 
 static void pch_smbus_init(device_t dev)
 {

src/soc/intel/broadwell/smbus_common.c

@@ -26,8 +26,8 @@
 #include <device/smbus_def.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/smbus.h>
+#include <soc/ramstage.h>
+#include <soc/smbus.h>
 
 static void smbus_delay(void)
 {

src/soc/intel/broadwell/smi.c

@@ -26,10 +26,10 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 #include <string.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pch.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 
 void southbridge_smm_clear_state(void)
 {

src/soc/intel/broadwell/smihandler.c

@@ -29,13 +29,13 @@
 #include <elog.h>
 #include <halt.h>
 #include <pc80/mc146818rtc.h>
-#include <broadwell/lpc.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/pm.h>
-#include <broadwell/rcba.h>
-#include <broadwell/smm.h>
-#include <broadwell/xhci.h>
+#include <soc/lpc.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/rcba.h>
+#include <soc/smm.h>
+#include <soc/xhci.h>
 
 static u8 smm_initialized = 0;
 

src/soc/intel/broadwell/smmrelocate.c

@@ -29,11 +29,11 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/smm.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <soc/smm.h>
+#include <soc/systemagent.h>
 
 /* This gets filled in and used during relocation. */
 static struct smm_relocation_params smm_reloc_params;

src/soc/intel/broadwell/spi.c

@@ -28,7 +28,7 @@
 #include <console/console.h>
 #include <device/pci_ids.h>
 #include <spi-generic.h>
-#include <broadwell/pci_devs.h>
+#include <soc/pci_devs.h>
 
 #ifdef __SMM__
 #define pci_read_config_byte(dev, reg, targ)\

src/soc/intel/broadwell/stage_cache.c

@@ -19,7 +19,7 @@
 
 #include <cbmem.h>
 #include <ramstage_cache.h>
-#include <broadwell/smm.h>
+#include <soc/smm.h>
 #include <stdint.h>
 
 struct ramstage_cache *ramstage_cache_location(long *size)

src/soc/intel/broadwell/systemagent.c

@@ -30,11 +30,11 @@
 #include <string.h>
 #include <cbmem.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <broadwell/cpu.h>
-#include <broadwell/iomap.h>
-#include <broadwell/pci_devs.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/systemagent.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/systemagent.h>
 
 u8 systemagent_revision(void)
 {

src/soc/intel/broadwell/tsc_freq.c

@@ -20,8 +20,8 @@
 #include <stdint.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <broadwell/cpu.h>
-#include <broadwell/msr.h>
+#include <soc/cpu.h>
+#include <soc/msr.h>
 
 unsigned long tsc_freq_mhz(void)
 {

src/soc/intel/broadwell/usbdebug.c

@@ -23,7 +23,7 @@
 #include <usbdebug.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
-#include <broadwell/pci_devs.h>
+#include <soc/pci_devs.h>
 
 void set_debug_port(unsigned int port)
 {

src/soc/intel/broadwell/xhci.c

@@ -23,9 +23,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
-#include <broadwell/ramstage.h>
-#include <broadwell/xhci.h>
-#include <broadwell/cpu.h>
+#include <soc/ramstage.h>
+#include <soc/xhci.h>
+#include <soc/cpu.h>
 
 #ifdef __SMM__
 static u8 *usb_xhci_mem_base(device_t dev)