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arm: Get rid of the INTERMEDIATE variable used on exynos. 

The INTERMEDIATE variable was used to hook dd-ing the BL1 into the image for
Exynos SOCs, but we can do that directly without having a special hook.

Change-Id: I434506b52ca4ea1d01e25a785cbfe66dfdea21c4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170921
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8db03c387ad654227d064e2a7fa5ecf09d07e3c5)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Gabe Black 2013-09-26 23:21:57 -07:00 committed by Isaac Christensen
parent cc95f18973
commit 4f3873d2ce
2 changed files with 10 additions and 10 deletions
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10
src/cpu/samsung/exynos5250/Makefile.inc
View File

@ -1,8 +1,3 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
INTERMEDIATE += exynos5250_add_bl1
bootblock-y += spi.c alternate_cbfs.c bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART # Clock is required for UART
@ -54,6 +49,11 @@ ramstage-y += fb.c
ramstage-y += usb.c ramstage-y += usb.c
ramstage-y += cbmem.c ramstage-y += cbmem.c
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
.PHONY: exynos5250_add_bl1
$(obj)/coreboot.rom: exynos5250_add_bl1
exynos5250_add_bl1: $(obj)/coreboot.pre exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n" printf " DD Adding Samsung Exynos5250 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \ dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \

10
src/cpu/samsung/exynos5420/Makefile.inc
View File

@ -1,8 +1,3 @@
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
INTERMEDIATE += exynos5420_add_bl1
bootblock-y += spi.c alternate_cbfs.c bootblock-y += spi.c alternate_cbfs.c
bootblock-y += pinmux.c mct.c power.c bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART # Clock is required for UART
@ -54,6 +49,11 @@ ramstage-y += dp.c dp_lowlevel.c fimd.c
ramstage-y += usb.c ramstage-y += usb.c
ramstage-y += cbmem.c ramstage-y += cbmem.c
# Run an intermediate step when producing coreboot.rom
# that adds additional components to the final firmware
# image outside of CBFS
.PHONY: exynos5420_add_bl1
$(obj)/coreboot.rom: exynos5420_add_bl1
exynos5420_add_bl1: $(obj)/coreboot.pre exynos5420_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5420 BL1\n" printf " DD Adding Samsung Exynos5420 BL1\n"
dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \ dd if=3rdparty/cpu/samsung/exynos5420/bl1.bin \