GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/strago: Disable unused devices. 

This change will disable unused devices in
device tree to improve boot performance.

TEST=Build/Flash CB and boot to OS.
verify Touch screen, Audio, WIFI and Track pad functionality.

Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/300943
Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/13423
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Divagar Mohandass 2015-09-21 11:51:07 +05:30 committed by Martin Roth
parent 97f09c3f19
commit 4f4c6e88be
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mainboard/intel/strago/devicetree.cb
View File

@ -28,11 +28,11 @@ chip soc/intel/braswell
register "PcdEnableDma1" = "1"
register "PcdEnableI2C0" = "1"
register "PcdEnableI2C1" = "1"
register "PcdEnableI2C2" = "1"
register "PcdEnableI2C3" = "1"
register "PcdEnableI2C2" = "0"
register "PcdEnableI2C3" = "0"
register "PcdEnableI2C4" = "1"
register "PcdEnableI2C5" = "1"
register "PcdEnableI2C6" = "1"
register "PcdEnableI2C6" = "0"
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_ACPI_MODE"
@ -94,7 +94,7 @@ chip soc/intel/braswell
# EDS Table 24-4, Figure 24-5
device pci 00.0 on end # 8086 2280 - SoC transaction router
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
device pci 03.0 on end # 8086 22b8 - Camera and Image Processor
device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
device pci 0b.0 on end # 8086 22dc - ?
device pci 10.0 on end # 8086 2294 - MMC Port
device pci 11.0 off end # 8086 0F15 - SDIO Port
@ -106,25 +106,25 @@ chip soc/intel/braswell
device pci 18.0 on end # 8086 22c0 - SIO - DMA
device pci 18.1 on end # 8086 22c1 - I2C Port 1
device pci 18.2 on end # 8086 22c2 - I2C Port 2
device pci 18.3 on end # 8086 22c3 - I2C Port 3
device pci 18.4 on end # 8086 22c4 - I2C Port 4
device pci 18.3 off end # 8086 22c3 - I2C Port 3
device pci 18.4 off end # 8086 22c4 - I2C Port 4
device pci 18.5 on end # 8086 22c5 - I2C Port 5
device pci 18.6 on end # 8086 22c6 - I2C Port 6
device pci 18.7 on end # 8086 22c7 - I2C Port 7
device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine
device pci 18.7 off end # 8086 22c7 - I2C Port 7
device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine
device pci 1b.0 on end # 8086 0F04 - HD Audio
device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1
device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2
device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3
device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4
device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4
device pci 1e.0 on end # 8086 2286 - SIO - DMA
device pci 1e.1 off end # 8086 0F08 - PWM 1
device pci 1e.2 off end # 8086 0F09 - PWM 2
device pci 1e.3 on end # 8086 228a - HSUART 1
device pci 1e.4 on end # 8086 228c - HSUART 2
device pci 1e.4 off end # 8086 228c - HSUART 2
device pci 1e.5 on end # 8086 228e - SPI 1
device pci 1e.6 on end # 8086 2290 - SPI 2
device pci 1e.7 on end # 8086 22ac - SPI 3
device pci 1e.6 off end # 8086 2290 - SPI 2
device pci 1e.7 off end # 8086 22ac - SPI 3
device pci 1f.0 on # 8086 229c - LPC bridge
chip drivers/pc80/tpm
# Rising edge interrupt