soc/intel/apollolake: Enabling using of MRC data when available
Change-Id: Iee30a6efb8dcdd04affd5d1105a254781287e9e4 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -23,6 +23,7 @@
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#include <device/resource.h>
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#include <device/resource.h>
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#include <string.h>
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#include <string.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/intel/common/mrc_cache.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/northbridge.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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@ -78,10 +79,10 @@ static void disable_watchdog(void)
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asmlinkage void car_stage_entry(void)
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asmlinkage void car_stage_entry(void)
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{
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{
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void *hob_list_ptr;
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void *hob_list_ptr, *mrc_data;
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struct range_entry fsp_mem;
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struct range_entry fsp_mem, reg_car;
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struct range_entry reg_car;
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struct postcar_frame pcf;
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struct postcar_frame pcf;
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size_t mrc_data_size;
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printk(BIOS_DEBUG, "Starting romstage...\n");
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printk(BIOS_DEBUG, "Starting romstage...\n");
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@ -111,6 +112,15 @@ asmlinkage void car_stage_entry(void)
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/* Now that CBMEM is up, save the list so ramstage can use it */
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/* Now that CBMEM is up, save the list so ramstage can use it */
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fsp_save_hob_list(hob_list_ptr);
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fsp_save_hob_list(hob_list_ptr);
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/* Save MRC Data to CBMEM */
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if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS))
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{
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/* TODO: treat MRC data as const */
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mrc_data = (void*) fsp_find_nv_storage_data(&mrc_data_size);
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if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0)
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printk(BIOS_ERR, "Failed to stash MRC data\n");
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}
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if (postcar_frame_init(&pcf, 1*KiB))
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if (postcar_frame_init(&pcf, 1*KiB))
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die("Unable to initialize postcar frame.\n");
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die("Unable to initialize postcar frame.\n");
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@ -134,6 +144,9 @@ static void fill_console_params(struct FSPM_UPD *mupd)
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void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
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void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
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{
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{
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const struct mrc_saved_data *mrc_cache;
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struct FSP_M_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
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fill_console_params(mupd);
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fill_console_params(mupd);
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mainboard_memory_init_params(mupd);
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mainboard_memory_init_params(mupd);
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@ -154,6 +167,18 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
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*/
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*/
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mupd->FspmArchUpd.StackBase = _car_region_end -
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mupd->FspmArchUpd.StackBase = _car_region_end -
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mupd->FspmArchUpd.StackSize;
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mupd->FspmArchUpd.StackSize;
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arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION;
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if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
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if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) {
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/* MRC cache found */
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arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
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arch_upd->Bootmode = FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
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printk(BIOS_DEBUG, "MRC cache found, size %x\n", mrc_cache->size);
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} else
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printk(BIOS_DEBUG, "MRC cache was not found\n");
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}
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}
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}
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__attribute__ ((weak))
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__attribute__ ((weak))
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