soc/intel/apollolake: Enable CACHE_MRC_SETTINGS

This enables CACHE_MRC_SETTINGS by default as well selects
timer configuration.

Change-Id: I0248001892ef763c39097848b5adc8c1befed1f0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14252
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/apollolake/Kconfig

@@ -35,8 +35,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SPI_FLASH
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
-	select UDELAY_TSC
-	select TSC_CONSTANT_RATE
+	select TSC_MONOTONIC_TIMER
+	select HAVE_MONOTONIC_TIMER
 	select PLATFORM_USES_FSP2_0
 
 config MMCONF_BASE_ADDRESS
@@ -100,4 +100,8 @@ config ROMSTAGE_ADDR
 	help
 	  The base address (in CAR) where romstage should be linked
 
+config CACHE_MRC_SETTINGS
+	bool
+	default y
+
 endif

src/soc/intel/apollolake/Makefile.inc

@@ -44,6 +44,7 @@ postcar-y += exit_car.S
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
 postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+postcar-y += tsc_freq.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include