mb/google/rex/variants/ovis: Add USB and TCSS configuration
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Jakub Czapiga
Subrata Banik
parent
07046ca217
commit
4fe0b40e1b
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@ -1,4 +1,18 @@
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chip soc/intel/meteorlake
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
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register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
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register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1
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register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2
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register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
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register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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@ -36,6 +50,128 @@ chip soc/intel/meteorlake
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end # PCIE11 SSD card
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp2 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
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register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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chip drivers/intel/usb4/retimer
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register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port2 as dfp[1].typec_port
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device generic 0 on end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port3 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
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register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))"
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register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A2""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(3, 3))"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A3""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(3, 4))"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))"
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register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
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device ref usb3_port2 on end
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end
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end
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end
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end
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device ref i2c4 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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@ -45,8 +181,32 @@ chip soc/intel/meteorlake
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end
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device ref soc_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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use conn2 as mux_conn[2]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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use usb2_port2 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port1 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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chip drivers/intel/pmc_mux/conn
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use usb2_port3 as usb2_port
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use tcss_usb3_port3 as usb3_port
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device generic 2 alias conn2 on end
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end
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end
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end
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end
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end
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end
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