AGESA f14: Remove OPTION_DDR2
Was never used for the boards in our tree. Change-Id: Ib9e9ab25ccb8d1d556fdeb8bb4c6558f25bb81b6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -298,23 +298,6 @@ BOOLEAN MemFS3DefConstructorRet (
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*
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*----------------------------------------------------------------------------------
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*/
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#if OPTION_DDR2 == TRUE
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extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
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#define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
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#if (OPTION_HW_DRAM_INIT == TRUE)
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extern MEM_TECH_FEAT MemTDramInitHw;
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#define MEM_TECH_FEATURE_HW_DRAMINIT MemTDramInitHw
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#else
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#define MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
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#endif
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#if (OPTION_SW_DRAM_INIT == TRUE)
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#define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
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#else
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#define MEM_TECH_FEATURE_SW_DRAMINIT MemTFeatDef
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#endif
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#else
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#define MEM_TECH_CONSTRUCTOR_DDR2
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#endif
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#if OPTION_DDR3 == TRUE
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extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
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#define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
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@ -347,10 +330,6 @@ BOOLEAN MemFS3DefConstructorRet (
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*---------------------------------------------------------------------------------------------------
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*/
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#if (OPTION_MEMCTLR_ON == TRUE)
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#if OPTION_DDR2
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#undef MEM_TECH_FEATURE_DRAMINIT
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#define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
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#endif
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#if OPTION_DDR3
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#undef MEM_TECH_FEATURE_DRAMINIT
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#define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
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@ -445,20 +424,6 @@ BOOLEAN MemFS3DefConstructorRet (
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#if OPTION_MEMCTLR_ON
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extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceON;
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#define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
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#define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
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#define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
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#define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
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#define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
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#define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
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#define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
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#define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
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#define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
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#define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
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#define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
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#define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
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#define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
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#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
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#if OPTION_DDR3
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#undef TECH_TRAIN_ENTER_HW_TRN_DDR3
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#define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
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@ -543,17 +508,11 @@ BOOLEAN MemFS3DefConstructorRet (
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#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
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#endif
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#else
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#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
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#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
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#endif
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#define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_ON
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MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
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MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON
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MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
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@ -564,6 +523,8 @@ BOOLEAN MemFS3DefConstructorRet (
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*
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*---------------------------------------------------------------------------------------------------
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*/
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#define NB_TRAIN_FLOW_DDR2 (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
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OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control
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NB_TRAIN_FLOW_DDR2,
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NB_TRAIN_FLOW_DDR3,
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@ -575,7 +536,6 @@ BOOLEAN MemFS3DefConstructorRet (
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*---------------------------------------------------------------------------------------------------
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*/
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MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed
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MEM_TECH_CONSTRUCTOR_DDR2
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MEM_TECH_CONSTRUCTOR_DDR3
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NULL
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};
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@ -624,11 +584,6 @@ BOOLEAN MemFS3DefConstructorRet (
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#if OPTION_MEMCTLR_ON
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#if OPTION_UDIMMS
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#if OPTION_DDR2
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#define PSC_ON_UDIMM_DDR2 //MemAGetPsCfgUON2,
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#else
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#define PSC_ON_UDIMM_DDR2
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#endif
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#if OPTION_DDR3
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#define PSC_ON_UDIMM_DDR3 MemAGetPsCfgUON3,
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#else
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@ -636,11 +591,6 @@ BOOLEAN MemFS3DefConstructorRet (
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#endif
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#endif
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#if OPTION_RDIMMS
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#if OPTION_DDR2
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#define PSC_ON_RDIMM_DDR2
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#else
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#define PSC_ON_RDIMM_DDR2
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#endif
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#if OPTION_DDR3
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#define PSC_ON_RDIMM_DDR3 //MemAGetPsCfgRON3,
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#else
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@ -648,11 +598,6 @@ BOOLEAN MemFS3DefConstructorRet (
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#endif
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#endif
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#if OPTION_SODIMMS
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#if OPTION_DDR2
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#define PSC_ON_SODIMM_DDR2 //MemAGetPsCfgSON2,
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#else
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#define PSC_ON_SODIMM_DDR2
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#endif
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#if OPTION_DDR3
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#define PSC_ON_SODIMM_DDR3 MemAGetPsCfgSON3,
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#else
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@ -780,14 +725,6 @@ BOOLEAN MemFS3DefConstructorRet (
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*
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*---------------------------------------------------------------------------------------------------
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*/
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#if OPTION_DDR2
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MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = {
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0
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};
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MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
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{ 0 }
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};
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#endif
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#if OPTION_DDR3
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MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = {
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0
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@ -141,7 +141,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
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#define OPTION_RDIMMS FALSE
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#define OPTION_SODIMMS FALSE
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#define OPTION_LRDIMMS FALSE
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#define OPTION_DDR2 FALSE
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#define OPTION_DDR3 FALSE
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#define OPTION_ECC FALSE
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#define OPTION_BANK_INTERLEAVE FALSE
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