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compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD 

make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Florian Zumbiehl 2011-11-01 20:17:41 +01:00 committed by Stefan Reinauer
parent be7d8dcf8d
commit 50dadfb1f8
2 changed files with 2 additions and 2 deletions
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2
src/southbridge/via/k8t890/romstrap.inc
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@ -33,7 +33,7 @@ __romstrap_start:
* Below are some Dev0 Func2 HT control registers values, * Below are some Dev0 Func2 HT control registers values,
* depending on strap pin, one of below lines is used. * depending on strap pin, one of below lines is used.
*/ */
#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 #if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
tblpointer: tblpointer:
.long 0x50220000, 0X619707C2 .long 0x50220000, 0X619707C2

2
src/southbridge/via/vt8237r/lpc.c
View File

@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev)
pci_write_config8(dev, 0x48, 0x0c); pci_write_config8(dev, 0x48, 0x0c);
#else #else
#if CONFIG_SOUTHBRIDGE_VIA_K8T800 #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
/* It seems that when we pair with the K8T800, we need to disable /* It seems that when we pair with the K8T800, we need to disable
* the A2 mask * the A2 mask
*/ */