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Nyans: replace cpu_reset with hard_reset 

The existing cpu_reset does board-wide reset, thus, should be renamed.

BUG=none
BRANCH=none
TEST=Built firmware for Nyans. Ran faft on Blaze.
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

Original-Change-Id: I5dc4fa9bae328001a897a371d4f23632701f1dd9
Original-Reviewed-on: https://chromium-review.googlesource.com/212982
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 29753b9c1dfe7ecd156042d69b74e9fe4244f455)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I98eca40c50637bda01a9029a904bca6880cd081f
Reviewed-on: http://review.coreboot.org/9179
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Daisuke Nojiri 2014-08-15 17:07:39 -07:00 committed by Stefan Reinauer
parent b71d9b8a0f
commit 512bfbc1c7
16 changed files with 22 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/nyan/Makefile.inc
View File

@ -38,6 +38,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

4
src/mainboard/google/nyan/pmic.c
View File

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (do_delay)
udelay(500);

5
src/mainboard/google/nyan/reset.c
View File

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan/reset.h
View File

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan/romstage.c
View File

@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/mainboard/google/nyan_big/Makefile.inc
View File

@ -37,6 +37,7 @@ romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += early_configs.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

4
src/mainboard/google/nyan_big/pmic.c
View File

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (do_delay)
udelay(500);

5
src/mainboard/google/nyan_big/reset.c
View File

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan_big/reset.h
View File

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan_big/romstage.c
View File

@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -79,7 +79,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/mainboard/google/nyan_blaze/Makefile.inc
View File

@ -41,6 +41,7 @@ romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

4
src/mainboard/google/nyan_blaze/pmic.c
View File

@ -26,7 +26,7 @@
#include <boardid.h>
#include "pmic.h"
#include "reset.h"
#include <reset.h>
enum {
AS3722_I2C_ADDR = 0x40
@ -65,7 +65,7 @@ static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
__func__, reg, val);
/* Reset the SoC on any PMIC write error */
cpu_reset();
hard_reset();
} else {
if (do_delay)
udelay(500);

5
src/mainboard/google/nyan_blaze/reset.c
View File

@ -19,10 +19,9 @@
#include <arch/io.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <reset.h>
#include "reset.h"
void cpu_reset(void)
void hard_reset(void)
{
gpio_output(GPIO(I5), 0);
while(1);

25
src/mainboard/google/nyan_blaze/reset.h
View File

@ -1,25 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
#define __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__
void cpu_reset(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BOOTBLOCK_H__ */

4
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -24,7 +24,7 @@
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <mainboard/google/nyan/reset.h>
#include <reset.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
@ -82,7 +82,7 @@ static void __attribute__((noinline)) romstage(void)
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
cpu_reset();
hard_reset();
}
cbmem_initialize_empty();

1
src/soc/nvidia/tegra124/Kconfig
View File

@ -6,6 +6,7 @@ config SOC_NVIDIA_TEGRA124
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select HAVE_UART_SPECIAL
select HAVE_HARD_RESET
select BOOTBLOCK_CONSOLE
select ARM_BOOTBLOCK_CUSTOM
select ARM_LPAE