soc/intel/cannonlake: Clear EMMC timeout register

Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.

BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.

Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Lijian Zhao 2018-02-20 14:37:03 -08:00 committed by Patrick Georgi
parent 9672b54087
commit 51605e2c9e
2 changed files with 13 additions and 3 deletions

View File

@ -13,6 +13,8 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <soc/pcr_ids.h>
Scope (\_SB.PCI0) { Scope (\_SB.PCI0) {
/* EMMC */ /* EMMC */
Device(PEMC) { Device(PEMC) {
@ -34,6 +36,10 @@ Scope (\_SB.PCI0) {
Store(0, PGEN) // Disable PG Store(0, PGEN) // Disable PG
/* Clear register 0x1C20/0x4820 */
^^PCRA (PID_EMMC, 0x1C20, 0x0)
^^PCRA (PID_EMMC, 0x4820, 0x0)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP) Store (PMCR, ^TEMP)
@ -78,6 +84,10 @@ Scope (\_SB.PCI0) {
{ {
Store (0, PGEN) /* Disable PG */ Store (0, PGEN) /* Disable PG */
/* Clear register 0x1C20/0x4820 */
^^PCRA (PID_SDX, 0x1C20, 0x0)
^^PCRA (PID_SDX, 0x4820, 0x0)
/* Set Power State to D0 */ /* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR) And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP) Store (PMCR, ^TEMP)

View File

@ -19,12 +19,12 @@
/* PCI IRQ assignment */ /* PCI IRQ assignment */
#include "pci_irqs.asl" #include "pci_irqs.asl"
/* eMMC, SD Card */
#include "scs.asl"
/* PCR access */ /* PCR access */
#include <soc/intel/common/acpi/pcr.asl> #include <soc/intel/common/acpi/pcr.asl>
/* eMMC, SD Card */
#include "scs.asl"
/* GPIO controller */ /* GPIO controller */
#include "gpio.asl" #include "gpio.asl"