soc/intel/cannonlake: Clear EMMC timeout register
Clear EMMC timeout register to avoid EMMC issue according to cannonlake bios writer guide. BUG=b.71586766 TEST=Install OS into EMMC successfully on meowth P1 platform. Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -13,6 +13,8 @@
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* GNU General Public License for more details.
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* GNU General Public License for more details.
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*/
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*/
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#include <soc/pcr_ids.h>
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Scope (\_SB.PCI0) {
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Scope (\_SB.PCI0) {
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/* EMMC */
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/* EMMC */
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Device(PEMC) {
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Device(PEMC) {
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@ -34,6 +36,10 @@ Scope (\_SB.PCI0) {
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Store(0, PGEN) // Disable PG
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Store(0, PGEN) // Disable PG
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/* Clear register 0x1C20/0x4820 */
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^^PCRA (PID_EMMC, 0x1C20, 0x0)
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^^PCRA (PID_EMMC, 0x4820, 0x0)
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/* Set Power State to D0 */
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/* Set Power State to D0 */
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And (PMCR, 0xFFFC, PMCR)
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And (PMCR, 0xFFFC, PMCR)
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Store (PMCR, ^TEMP)
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Store (PMCR, ^TEMP)
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@ -78,6 +84,10 @@ Scope (\_SB.PCI0) {
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{
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{
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Store (0, PGEN) /* Disable PG */
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Store (0, PGEN) /* Disable PG */
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/* Clear register 0x1C20/0x4820 */
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^^PCRA (PID_SDX, 0x1C20, 0x0)
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^^PCRA (PID_SDX, 0x4820, 0x0)
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/* Set Power State to D0 */
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/* Set Power State to D0 */
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And (PMCR, 0xFFFC, PMCR)
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And (PMCR, 0xFFFC, PMCR)
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Store (PMCR, ^TEMP)
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Store (PMCR, ^TEMP)
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@ -19,12 +19,12 @@
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/* PCI IRQ assignment */
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/* PCI IRQ assignment */
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#include "pci_irqs.asl"
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#include "pci_irqs.asl"
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/* eMMC, SD Card */
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#include "scs.asl"
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/* PCR access */
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/* PCR access */
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#include <soc/intel/common/acpi/pcr.asl>
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#include <soc/intel/common/acpi/pcr.asl>
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/* eMMC, SD Card */
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#include "scs.asl"
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/* GPIO controller */
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/* GPIO controller */
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#include "gpio.asl"
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#include "gpio.asl"
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