soc/intel/cannonlake: Clear EMMC timeout register

Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide.

BUG=b.71586766
TEST=Install OS into EMMC successfully on meowth P1 platform.

Change-Id: I39e927a2c312c94561213f9f7c3319dcafa426b9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/cannonlake/acpi/scs.asl

@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <soc/pcr_ids.h>
+
 Scope (\_SB.PCI0) {
 	/* EMMC */
 	Device(PEMC) {
@@ -34,6 +36,10 @@ Scope (\_SB.PCI0) {
 
 			Store(0, PGEN) // Disable PG
 
+			/* Clear register 0x1C20/0x4820 */
+			^^PCRA (PID_EMMC, 0x1C20, 0x0)
+			^^PCRA (PID_EMMC, 0x4820, 0x0)
+
 			/* Set Power State to D0 */
 			And (PMCR, 0xFFFC, PMCR)
 			Store (PMCR, ^TEMP)
@@ -78,6 +84,10 @@ Scope (\_SB.PCI0) {
 		{
 			Store (0, PGEN) /* Disable PG */
 
+			/* Clear register 0x1C20/0x4820 */
+			^^PCRA (PID_SDX, 0x1C20, 0x0)
+			^^PCRA (PID_SDX, 0x4820, 0x0)
+
 			/* Set Power State to D0 */
 			And (PMCR, 0xFFFC, PMCR)
 			Store (PMCR, ^TEMP)

src/soc/intel/cannonlake/acpi/southbridge.asl

@@ -19,12 +19,12 @@
 /* PCI IRQ assignment */
 #include "pci_irqs.asl"
 
-/* eMMC, SD Card */
-#include "scs.asl"
-
 /* PCR access */
 #include <soc/intel/common/acpi/pcr.asl>
 
+/* eMMC, SD Card */
+#include "scs.asl"
+
 /* GPIO controller */
 #include "gpio.asl"