soc/amd/picasso,stoneyridge/mca: clean up mca_bank struct
Only the fields bank and sts from the mca_bank struct were used outside a local scope, so remove the rest. Also rename the struct that now only contains the bank number and the status MSR content to mca_bank_status. Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -13,13 +13,9 @@
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/* MISC4 is the last used register in the MCAX banks of Picasso */
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#define MCAX_USED_REGISTERS_PER_BANK (MCAX_MISC4_OFFSET + 1)
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struct mca_bank {
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struct mca_bank_status {
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int bank;
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msr_t ctl;
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msr_t sts;
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msr_t addr;
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msr_t misc;
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msr_t cmask;
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};
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static inline size_t mca_report_size_reqd(void)
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@ -50,7 +46,7 @@ static inline size_t mca_report_size_reqd(void)
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return size;
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}
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static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci)
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static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci)
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{
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int error = mca_err_type(mci->sts);
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@ -68,7 +64,7 @@ static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci)
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/* Fill additional information in the Generic Processor Error Section. */
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static void fill_generic_section(cper_proc_generic_error_section_t *sec,
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struct mca_bank *mci)
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struct mca_bank_status *mci)
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{
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int type = mca_err_type(mci->sts);
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@ -91,7 +87,7 @@ static void fill_generic_section(cper_proc_generic_error_section_t *sec,
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* structures: A "processor generic error" that is parsed, and an IA32/X64 one
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* to capture complete information.
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*/
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static void build_bert_mca_error(struct mca_bank *mci)
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static void build_bert_mca_error(struct mca_bank_status *mci)
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{
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acpi_generic_error_status_t *status;
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acpi_hest_generic_data_v300_t *gen_entry;
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@ -153,7 +149,8 @@ static const char *const mca_bank_name[] = {
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void check_mca(void)
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{
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int i;
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struct mca_bank mci;
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struct mca_bank_status mci;
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msr_t msr;
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const unsigned int num_banks = mca_get_bank_count();
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for (i = 0 ; i < num_banks ; i++) {
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@ -165,18 +162,18 @@ void check_mca(void)
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printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",
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i, mci.sts.hi, mci.sts.lo);
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mci.addr = rdmsr(MCAX_ADDR_MSR(i));
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msr = rdmsr(MCAX_ADDR_MSR(i));
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printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",
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i, mci.addr.hi, mci.addr.lo);
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mci.misc = rdmsr(MCAX_MISC0_MSR(i));
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i, msr.hi, msr.lo);
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msr = rdmsr(MCAX_MISC0_MSR(i));
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printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",
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i, mci.misc.hi, mci.misc.lo);
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mci.ctl = rdmsr(MCAX_CTL_MSR(i));
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i, msr.hi, msr.lo);
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msr = rdmsr(MCAX_CTL_MSR(i));
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printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n",
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i, mci.ctl.hi, mci.ctl.lo);
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mci.cmask = rdmsr(MCA_CTL_MASK_MSR(i));
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i, msr.hi, msr.lo);
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msr = rdmsr(MCA_CTL_MASK_MSR(i));
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printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",
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i, mci.cmask.hi, mci.cmask.lo);
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i, msr.hi, msr.lo);
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mci.bank = i;
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if (CONFIG(ACPI_BERT) && mca_valid(mci.sts))
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@ -185,8 +182,8 @@ void check_mca(void)
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}
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/* zero the machine check error status registers */
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mci.sts.lo = 0;
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mci.sts.hi = 0;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0 ; i < num_banks ; i++)
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wrmsr(MCAX_STATUS_MSR(i), mci.sts);
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wrmsr(MCAX_STATUS_MSR(i), msr);
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}
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@ -9,13 +9,9 @@
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#include <arch/bert_storage.h>
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#include <cper.h>
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struct mca_bank {
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struct mca_bank_status {
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int bank;
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msr_t ctl;
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msr_t sts;
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msr_t addr;
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msr_t misc;
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msr_t cmask;
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};
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static inline size_t mca_report_size_reqd(void)
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@ -45,7 +41,7 @@ static inline size_t mca_report_size_reqd(void)
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return size;
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}
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static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci)
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static enum cper_x86_check_type error_to_chktype(struct mca_bank_status *mci)
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{
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int error = mca_err_type(mci->sts);
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@ -63,7 +59,7 @@ static enum cper_x86_check_type error_to_chktype(struct mca_bank *mci)
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/* Fill additional information in the Generic Processor Error Section. */
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static void fill_generic_section(cper_proc_generic_error_section_t *sec,
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struct mca_bank *mci)
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struct mca_bank_status *mci)
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{
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int type = mca_err_type(mci->sts);
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@ -91,7 +87,7 @@ static void fill_generic_section(cper_proc_generic_error_section_t *sec,
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* Processor Generic section and the failing error/check added to the
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* IA32/X64 section.
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*/
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static void build_bert_mca_error(struct mca_bank *mci)
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static void build_bert_mca_error(struct mca_bank_status *mci)
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{
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acpi_generic_error_status_t *status;
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acpi_hest_generic_data_v300_t *gen_entry;
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@ -152,7 +148,8 @@ static const char *const mca_bank_name[] = {
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void check_mca(void)
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{
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int i;
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struct mca_bank mci;
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struct mca_bank_status mci;
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msr_t msr;
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const unsigned int num_banks = mca_get_bank_count();
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if (is_warm_reset()) {
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@ -167,18 +164,18 @@ void check_mca(void)
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printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n",
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i, mci.sts.hi, mci.sts.lo);
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mci.addr = rdmsr(IA32_MC0_ADDR + (i * 4));
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msr = rdmsr(IA32_MC0_ADDR + (i * 4));
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printk(BIOS_WARNING, " MC%d_ADDR = %08x_%08x\n",
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i, mci.addr.hi, mci.addr.lo);
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mci.misc = rdmsr(IA32_MC0_MISC + (i * 4));
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i, msr.hi, msr.lo);
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msr = rdmsr(IA32_MC0_MISC + (i * 4));
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printk(BIOS_WARNING, " MC%d_MISC = %08x_%08x\n",
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i, mci.misc.hi, mci.misc.lo);
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mci.ctl = rdmsr(IA32_MC0_CTL + (i * 4));
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i, msr.hi, msr.lo);
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msr = rdmsr(IA32_MC0_CTL + (i * 4));
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printk(BIOS_WARNING, " MC%d_CTL = %08x_%08x\n",
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i, mci.ctl.hi, mci.ctl.lo);
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mci.cmask = rdmsr(MC0_CTL_MASK + i);
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i, msr.hi, msr.lo);
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msr = rdmsr(MC0_CTL_MASK + i);
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printk(BIOS_WARNING, " MC%d_CTL_MASK = %08x_%08x\n",
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i, mci.cmask.hi, mci.cmask.lo);
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i, msr.hi, msr.lo);
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mci.bank = i;
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if (CONFIG(ACPI_BERT) && mca_valid(mci.sts))
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@ -188,8 +185,8 @@ void check_mca(void)
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}
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/* zero the machine check error status registers */
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mci.sts.lo = 0;
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mci.sts.hi = 0;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0 ; i < num_banks ; i++)
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wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts);
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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}
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