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soc/intel/common: Skip SoC GT programming based on CONFIG_SKIP_GRAPHICS_ENABLING 

Skip GT specific programming in coreboot to support early
parts without GT enable.

Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-06-04 12:14:44 +05:30
parent 94cdec686e
commit 51b2fd82d3
2 changed files with 12 additions and 0 deletions
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8
src/soc/intel/common/block/graphics/Kconfig
View File

@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS
bool bool
help help
Intel Processor common Graphics support Intel Processor common Graphics support
config SKIP_GRAPHICS_ENABLING
bool
depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS
default n
help
Skip GT specific programming in coreboot to support
early parts without GT enable.

4
src/soc/intel/icelake/graphics.c
View File

@ -34,6 +34,10 @@ void graphics_soc_init(struct device *dev)
{ {
uint32_t ddi_buf_ctl; uint32_t ddi_buf_ctl;
/* Skip IGD GT programming */
if (CONFIG(SKIP_GRAPHICS_ENABLING))
return;
/* /*
* Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * Enable DDI-A (eDP) 4-lane operation if the link is not up yet.
* This will allow the kernel to use 4-lane eDP links properly * This will allow the kernel to use 4-lane eDP links properly