rambi/baytrail: ACPI, GPIO, audio, misc updates

rambi: Change RAM_ID GPIOs to GPIO_INPUT
Reviewed-on: https://chromium-review.googlesource.com/182934
(cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0)

baytrail: initialize rtc device
Reviewed-on: https://chromium-review.googlesource.com/183051
(cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821)

baytrail: Set SOC power budget values for SdpProfile 2&3
Reviewed-on: https://chromium-review.googlesource.com/183101
(cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55)

baytrail: Set PMC PTPS register correctly
Reviewed-on: https://chromium-review.googlesource.com/183280
(cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad)

baytrail: update to version 809 microcode for c0
Reviewed-on: https://chromium-review.googlesource.com/183256
(cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e)

baytrail: Add a shared GNVS init function
Reviewed-on: https://chromium-review.googlesource.com/183332
(cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c)

baytrail: Add basic support for ACPI System Wake Source
Reviewed-on: https://chromium-review.googlesource.com/183333
(cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619)

baytrail: allow configuration of io hole size
Reviewed-on: https://chromium-review.googlesource.com/183269
(cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919)

baytrail: add in C0 stepping idenitification support.
Reviewed-on: https://chromium-review.googlesource.com/183594
(cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4)

baytrail: add option for enabling PS2 mode
Reviewed-on: https://chromium-review.googlesource.com/183595
(cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f)

rambi: enable PS2 mode for VNN and VCC
Reviewed-on: https://chromium-review.googlesource.com/183596
(cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9)

baytrail: add config option for disabling slp_x stretching
Reviewed-on: https://chromium-review.googlesource.com/183587
(cherry picked from commit f99804c2649bef436644dd300be2a595659ceece)

rambi: disable slp_x stretching after sus fail
Reviewed-on: https://chromium-review.googlesource.com/183588
(cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880)

baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI
Reviewed-on: https://chromium-review.googlesource.com/183597
(cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906)

rambi: fix trackpad and touchscreen wake sources
Reviewed-on: https://chromium-review.googlesource.com/183598
(cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5)

baytrail: Add support for LPE device in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184006
(cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f)

rambi: Add LPE GPIOs for Jack/Mic detect
Reviewed-on: https://chromium-review.googlesource.com/184007
(cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578)

rambi: Set TSRx passive threshold to 60C
Reviewed-on: https://chromium-review.googlesource.com/184008
(cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee)

baytrail: DPTF: Add PPCC object for power limit information
Reviewed-on: https://chromium-review.googlesource.com/184158
(cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b)

baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant
Reviewed-on: https://chromium-review.googlesource.com/184442
(cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd)

rambi: Move the CPU passive/critical threshold config to DPTF
Reviewed-on: https://chromium-review.googlesource.com/184443
(cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac)

baytrail: Fix XHCI controller reset on resume
Reviewed-on: https://chromium-review.googlesource.com/184500
(cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd)

baytrail: update lpe audio firmware location
Reviewed-on: https://chromium-review.googlesource.com/184481
(cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6)

rambi: Put LPSS devices in ACPI mode
Reviewed-on: https://chromium-review.googlesource.com/184530
(cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1)

baytrail: initialize HDA device and HDMI codec
Reviewed-on: https://chromium-review.googlesource.com/184710
(cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961)

baytrail: provide GPIO_ACPI_WAKE configuration
Reviewed-on: https://chromium-review.googlesource.com/184718
(cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b)

rambi: configure wake pins as just wake sources
Reviewed-on: https://chromium-review.googlesource.com/184719
(cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115)

baytrail: I2C: Add config data to ACPI Device
Reviewed-on: https://chromium-review.googlesource.com/184922
(cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8)

Squashed 28 commits for rambi and baytrail.

Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Shawn Nematbakhsh 2014-01-16 17:52:21 -08:00 committed by Isaac Christensen
parent 1f279b68b6
commit 51d787a5cf
42 changed files with 13780 additions and 13149 deletions

View File

@ -1,16 +1,19 @@
#define DPTF_CPU_PASSIVE 60
#define DPTF_CPU_CRITICAL 70
#define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
#define DPTF_TSR0_PASSIVE 40 #define DPTF_TSR0_PASSIVE 60
#define DPTF_TSR0_CRITICAL 70 #define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 45 #define DPTF_TSR1_PASSIVE 60
#define DPTF_TSR1_CRITICAL 70 #define DPTF_TSR1_CRITICAL 70
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR2_PASSIVE 35 #define DPTF_TSR2_PASSIVE 60
#define DPTF_TSR2_CRITICAL 70 #define DPTF_TSR2_CRITICAL 70
#undef DPTF_ENABLE_CHARGER #undef DPTF_ENABLE_CHARGER
@ -22,6 +25,11 @@ Name (DTRT, Package () {
/* CPU Effect on Temp Sensor 0 */ /* CPU Effect on Temp Sensor 0 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 },
#ifdef DPTF_ENABLE_CHARGER
/* Charger Effect on Temp Sensor 1 */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 },
#endif
/* CPU Effect on Temp Sensor 1 */ /* CPU Effect on Temp Sensor 1 */
Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 },

View File

@ -360,3 +360,17 @@ Scope (\_SB.I2C6)
Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
} }
} }
Scope (\_SB.LPEA)
{
Name (GBUF, ResourceTemplate ()
{
/* Jack Detect (index 0) */
GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
"\\_SB.GPSC") { 14 }
/* Mic Detect (index 1) */
GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
"\\_SB.GPSC") { 15 }
})
}

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@ -1,245 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Thermal Zone
Scope (\_TZ)
{
ThermalZone (THRM)
{
Name (_TC1, 0x02)
Name (_TC2, 0x05)
// Thermal zone polling frequency: 0 seconds
Name (_TZP, 0)
// Thermal sampling period for passive cooling: 2 seconds
Name (_TSP, 20)
// Convert from Degrees C to 1/10 Kelvin for ACPI
Method (CTOK, 1) {
// 10th of Degrees C
Multiply (Arg0, 10, Local0)
// Convert to Kelvin
Add (Local0, 2732, Local0)
Return (Local0)
}
// Threshold for OS to shutdown
Method (_CRT, 0, Serialized)
{
Return (CTOK (\TCRT))
}
// Threshold for passive cooling
Method (_PSV, 0, Serialized)
{
Return (CTOK (\TPSV))
}
// Processors used for passive cooling
Method (_PSL, 0, Serialized)
{
Return (\PPKG ())
}
Method (_TMP, 0, Serialized)
{
Return (CTOK (30))
}
Method (_AC0) {
If (LLessEqual (\FLVL, 0)) {
Return (CTOK (\F0OF))
} Else {
Return (CTOK (\F0ON))
}
}
Method (_AC1) {
If (LLessEqual (\FLVL, 1)) {
Return (CTOK (\F1OF))
} Else {
Return (CTOK (\F1ON))
}
}
Method (_AC2) {
If (LLessEqual (\FLVL, 2)) {
Return (CTOK (\F2OF))
} Else {
Return (CTOK (\F2ON))
}
}
Method (_AC3) {
If (LLessEqual (\FLVL, 3)) {
Return (CTOK (\F3OF))
} Else {
Return (CTOK (\F3ON))
}
}
Method (_AC4) {
If (LLessEqual (\FLVL, 4)) {
Return (CTOK (\F4OF))
} Else {
Return (CTOK (\F4ON))
}
}
Name (_AL0, Package () { FAN0 })
Name (_AL1, Package () { FAN1 })
Name (_AL2, Package () { FAN2 })
Name (_AL3, Package () { FAN3 })
Name (_AL4, Package () { FAN4 })
PowerResource (FNP0, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 0)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (0, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (1, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
PowerResource (FNP1, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 1)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (1, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (2, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
PowerResource (FNP2, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 2)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (2, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (3, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
PowerResource (FNP3, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 3)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (3, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (4, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
PowerResource (FNP4, 0, 0)
{
Method (_STA) {
If (LLessEqual (\FLVL, 4)) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
Store (4, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
Store (4, \FLVL)
Notify (\_TZ.THRM, 0x81)
}
}
Device (FAN0)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 0)
Name (_PR0, Package () { FNP0 })
}
Device (FAN1)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 1)
Name (_PR0, Package () { FNP1 })
}
Device (FAN2)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 2)
Name (_PR0, Package () { FNP2 })
}
Device (FAN3)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 3)
Name (_PR0, Package () { FNP3 })
}
Device (FAN4)
{
Name (_HID, EISAID ("PNP0C0B"))
Name (_UID, 4)
Name (_PR0, Package () { FNP4 })
}
}
}

View File

@ -30,19 +30,15 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <baytrail/acpi.h> #include <baytrail/acpi.h>
#include <baytrail/nvs.h> #include <baytrail/nvs.h>
#include <baytrail/iomap.h> #include <baytrail/iomap.h>
#include "thermal.h"
extern const unsigned char AmlCode[]; extern const unsigned char AmlCode[];
static void acpi_create_gnvs(global_nvs_t *gnvs) static void acpi_create_gnvs(global_nvs_t *gnvs)
{ {
gnvs->pcnt = dev_count_cpu(); acpi_init_gnvs(gnvs);
/* Enable USB ports in S3 */ /* Enable USB ports in S3 */
gnvs->s3u0 = 1; gnvs->s3u0 = 1;
@ -52,26 +48,11 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0; gnvs->s5u0 = 0;
gnvs->s5u1 = 0; gnvs->s5u1 = 0;
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
/* TPM Present */ /* TPM Present */
gnvs->tpmp = 1; gnvs->tpmp = 1;
/* Enable DPTF */ /* Enable DPTF */
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
gnvs->tact = ACTIVE_TEMPERATURE;
gnvs->dpte = 1; gnvs->dpte = 1;
#if CONFIG_CHROMEOS
chromeos_init_vboot(&(gnvs->chromeos));
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
} }
unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_madt(unsigned long current)

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@ -33,6 +33,7 @@ chip soc/intel/baytrail
# Enable devices in ACPI mode # Enable devices in ACPI mode
register "scc_acpi_mode" = "1" register "scc_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
# Enable PIPEA as DP_C # Enable PIPEA as DP_C
register "gpu_pipea_hotplug" = "6" # 6ms Pulse register "gpu_pipea_hotplug" = "6" # 6ms Pulse
@ -44,6 +45,13 @@ chip soc/intel/baytrail
register "gpu_pipea_light_off_delay" = "2000" # 200ms register "gpu_pipea_light_off_delay" = "2000" # 200ms
register "gpu_pipea_backlight_pwm" = "0x400" register "gpu_pipea_backlight_pwm" = "0x400"
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end

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@ -35,8 +35,6 @@ DefinitionBlock(
// global NVS and variables // global NVS and variables
#include <soc/intel/baytrail/acpi/globalnvs.asl> #include <soc/intel/baytrail/acpi/globalnvs.asl>
//#include "acpi/thermal.asl"
#include <soc/intel/baytrail/acpi/cpu.asl> #include <soc/intel/baytrail/acpi/cpu.asl>
Scope (\_SB) { Scope (\_SB) {

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@ -163,9 +163,9 @@ static const struct soc_gpio_map gpscore_gpio_map[] = {
/* SSUS GPIOs */ /* SSUS GPIOs */
static const struct soc_gpio_map gpssus_gpio_map[] = { static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
@ -200,9 +200,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = {
GPIO_NC, /* S534 - NC */ GPIO_NC, /* S534 - NC */
GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
GPIO_NC, /* S536 - NC */ GPIO_NC, /* S536 - NC */
GPIO_FUNC0, /* S537 - RAM_ID0 */ GPIO_INPUT, /* S537 - RAM_ID0 */
GPIO_FUNC0, /* S538 - RAM_ID1 */ GPIO_INPUT, /* S538 - RAM_ID1 */
GPIO_FUNC0, /* S539 - RAM_ID2 */ GPIO_INPUT, /* S539 - RAM_ID2 */
GPIO_NC, /* S540 - NC */ GPIO_NC, /* S540 - NC */
GPIO_NC, /* S541 - NC */ GPIO_NC, /* S541 - NC */
GPIO_NC, /* S542 - NC */ GPIO_NC, /* S542 - NC */

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@ -19,6 +19,7 @@
#include <soc/intel/baytrail/baytrail/irq.h> #include <soc/intel/baytrail/baytrail/irq.h>
#include <soc/intel/baytrail/baytrail/pci_devs.h> #include <soc/intel/baytrail/baytrail/pci_devs.h>
#include <soc/intel/baytrail/baytrail/pmc.h>
#define PCI_DEV_PIRQ_ROUTES \ #define PCI_DEV_PIRQ_ROUTES \
PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \

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@ -24,13 +24,13 @@
#define BOARD_TRACKPAD_NAME "trackpad" #define BOARD_TRACKPAD_NAME "trackpad"
#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) #define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ #define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
#define BOARD_TRACKPAD_I2C_BUS 0 #define BOARD_TRACKPAD_I2C_BUS 0
#define BOARD_TRACKPAD_I2C_ADDR 0x4b #define BOARD_TRACKPAD_I2C_ADDR 0x4b
#define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_NAME "touchscreen"
#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) #define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ #define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
#define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_BUS 5
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */

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@ -49,6 +49,8 @@ ramstage-y += perf_power.c
ramstage-y += stage_cache.c ramstage-y += stage_cache.c
romstage-y += stage_cache.c romstage-y += stage_cache.c
ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += hda.c
ramstage-y += hda_verb.c
# Remove as ramstage gets fleshed out # Remove as ramstage gets fleshed out
ramstage-y += placeholders.c ramstage-y += placeholders.c

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@ -22,6 +22,7 @@
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <console/console.h> #include <console/console.h>
@ -39,6 +40,9 @@
#include <baytrail/pattrs.h> #include <baytrail/pattrs.h>
#include <baytrail/pmc.h> #include <baytrail/pmc.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#define MWAIT_RES(state, sub_state) \ #define MWAIT_RES(state, sub_state) \
{ \ { \
.addrl = (((state) << 4) | (sub_state)), \ .addrl = (((state) << 4) | (sub_state)), \
@ -74,6 +78,32 @@ static acpi_cstate_t cstate_map[] = {
} }
}; };
void acpi_init_gnvs(global_nvs_t *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
/* Top of Low Memory (start of resource allocation) */
gnvs->tolm = nc_read_top_of_low_memory();
#if CONFIG_CONSOLE_CBMEM
/* Update the mem console pointer. */
gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
#endif
#if CONFIG_CHROMEOS
/* Initialize Verified Boot data */
chromeos_init_vboot(&(gnvs->chromeos));
#if CONFIG_EC_GOOGLE_CHROMEEC
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
#endif
}
static int acpi_sci_irq(void) static int acpi_sci_irq(void)
{ {
const unsigned long actl = ILB_BASE_ADDRESS + ACTL; const unsigned long actl = ILB_BASE_ADDRESS + ACTL;

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@ -123,4 +123,39 @@ Device (TCPU)
Return (0) Return (0)
} }
} }
Name (PPCC, Package ()
{
0x2, // Revision
Package () { // Power Limit 1
0, // PowerLimitIndex, 0 for Power Limit 1
1600, // PowerLimitMinimum
6200, // PowerLimitMaximum
1000, // TimeWindowMinimum
1000, // TimeWindowMaximum
200 // StepSize
},
Package () { // Power Limit 2
1, // PowerLimitIndex, 1 for Power Limit 2
8000, // PowerLimitMinimum
8000, // PowerLimitMaximum
1000, // TimeWindowMinimum
1000, // TimeWindowMaximum
1000 // StepSize
}
})
#ifdef DPTF_CPU_CRITICAL
Method (_CRT)
{
Return (^^CTOK (DPTF_CPU_CRITICAL))
}
#endif
#ifdef DPTF_CPU_PASSIVE
Method (_PSV)
{
Return (^^CTOK (DPTF_CPU_PASSIVE))
}
#endif
} }

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@ -52,6 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TPMP, 8, // 0x12 - TPM Present and Enabled TPMP, 8, // 0x12 - TPM Present and Enabled
TLVL, 8, // 0x13 - Throttle Level TLVL, 8, // 0x13 - Throttle Level
PPCM, 8, // 0x14 - Maximum P-state usable by OS PPCM, 8, // 0x14 - Maximum P-state usable by OS
PM1I, 32, // 0x15 - System Wake Source - PM1 Index
/* Device Config */ /* Device Config */
Offset (0x20), Offset (0x20),

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@ -0,0 +1,119 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
Device (LPEA)
{
Name (_HID, "80860F28")
Name (_CID, "80860F28")
Name (_UID, 1)
Name (_DDN, "Low Power Audio Controller")
Name (_PR0, Package () { PLPE })
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0)
Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1)
Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2)
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_DMA0_IRQ
}
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_DMA1_IRQ
}
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_SSP0_IRQ
}
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_SSP1_IRQ
}
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_SSP2_IRQ
}
Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,)
{
LPE_IPC2HOST_IRQ
}
})
Method (_CRS)
{
/* Update BAR0 from NVS */
CreateDwordField (^RBUF, ^BAR0._BAS, BAS0)
Store (\LPB0, BAS0)
/* Update BAR1 from NVS */
CreateDwordField (^RBUF, ^BAR1._BAS, BAS1)
Store (\LPB1, BAS1)
/* Update LPE FW from NVS */
CreateDwordField (^RBUF, ^BAR2._BAS, BAS2)
Store (\LPFW, BAS2)
/* Append any Mainboard defined GPIOs */
If (CondRefOf (^GBUF, Local0)) {
ConcatenateResTemplate (^RBUF, Local0, Local1)
Return (Local1)
}
Return (^RBUF)
}
Method (_STA)
{
If (LEqual (\LPEN, 1)) {
Return (0xF)
} Else {
Return (0x0)
}
}
OperationRegion (KEYS, SystemMemory, LPB1, 0x100)
Field (KEYS, DWordAcc, NoLock, WriteAsZeros)
{
Offset (0x84),
PSAT, 32,
}
PowerResource (PLPE, 0, 0)
{
Method (_STA)
{
Return (1)
}
Method (_OFF)
{
Or (PSAT, 0x00000003, PSAT)
Or (PSAT, 0x00000000, PSAT)
}
Method (_ON)
{
And (PSAT, 0xfffffffc, PSAT)
Or (PSAT, 0x00000000, PSAT)
}
}
}

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@ -89,6 +89,12 @@ Device (I2C1)
Name (_UID, 1) Name (_UID, 1)
Name (_DDN, "I2C Controller #1") Name (_DDN, "I2C Controller #1")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -142,6 +148,12 @@ Device (I2C2)
Name (_UID, 2) Name (_UID, 2)
Name (_DDN, "I2C Controller #2") Name (_DDN, "I2C Controller #2")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -195,6 +207,12 @@ Device (I2C3)
Name (_UID, 3) Name (_UID, 3)
Name (_DDN, "I2C Controller #3") Name (_DDN, "I2C Controller #3")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -248,6 +266,12 @@ Device (I2C4)
Name (_UID, 4) Name (_UID, 4)
Name (_DDN, "I2C Controller #4") Name (_DDN, "I2C Controller #4")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -301,6 +325,12 @@ Device (I2C5)
Name (_UID, 5) Name (_UID, 5)
Name (_DDN, "I2C Controller #5") Name (_DDN, "I2C Controller #5")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -354,6 +384,12 @@ Device (I2C6)
Name (_UID, 6) Name (_UID, 6)
Name (_DDN, "I2C Controller #6") Name (_DDN, "I2C Controller #6")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)
@ -407,6 +443,12 @@ Device (I2C7)
Name (_UID, 7) Name (_UID, 7)
Name (_DDN, "I2C Controller #7") Name (_DDN, "I2C Controller #7")
/* Standard Mode: HCNT, LCNT, SDA Hold Time */
Name (SSCN, Package () { 0x200, 0x200, 0x6 })
/* Fast Mode: HCNT, LCNT, SDA Hold Time */
Name (FMCN, Package () { 0x55, 0x99, 0x6 })
Name (RBUF, ResourceTemplate() Name (RBUF, ResourceTemplate()
{ {
Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) Memory32Fixed (ReadWrite, 0, 0x1000, BAR0)

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@ -70,3 +70,9 @@ Method(_WAK,1)
{ {
Return(Package(){0,0}) Return(Package(){0,0})
} }
Method (_SWS)
{
/* Index into PM1 for device that caused wake */
Return (\PM1I)
}

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@ -268,4 +268,7 @@ Scope (\_SB)
// SCC Devices // SCC Devices
#include "scc.asl" #include "scc.asl"
// LPE Device
#include "lpe.asl"
} }

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@ -21,9 +21,11 @@
#define _BAYTRAIL_ACPI_H_ #define _BAYTRAIL_ACPI_H_
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baytrail/nvs.h>
void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_fill_in_fadt(acpi_fadt_t *fadt); void acpi_fill_in_fadt(acpi_fadt_t *fadt);
unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long acpi_madt_irq_overrides(unsigned long current);
void acpi_init_gnvs(global_nvs_t *gnvs);
#endif /* _BAYTRAIL_ACPI_H_ */ #endif /* _BAYTRAIL_ACPI_H_ */

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@ -229,8 +229,17 @@
#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) #define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K)
/* ACPI GPIO routing. Assume everything is externally pulled and negative edge /* ACPI GPIO routing. Assume everything is externally pulled and negative edge
* triggered. */ * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */
#define GPIO_ACPI_SCI \ #define GPIO_ACPI_SCI \
{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \
.use_sel = GPIO_USE_LEGACY, \
.io_sel = GPIO_DIR_INPUT, \
.tne = 1, \
.sci = 1, \
.wake_en = 1, }
#define GPIO_ACPI_WAKE \
{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \
.pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \
.pad_val = PAD_VAL_INPUT, \ .pad_val = PAD_VAL_INPUT, \
@ -281,14 +290,15 @@ struct soc_gpio_map {
u32 pad_conf0; u32 pad_conf0;
u32 pad_conf1; u32 pad_conf1;
u32 pad_val; u32 pad_val;
u8 use_sel : 1; u32 use_sel : 1;
u8 io_sel : 1; u32 io_sel : 1;
u8 gp_lvl : 1; u32 gp_lvl : 1;
u8 tpe : 1; u32 tpe : 1;
u8 tne : 1; u32 tne : 1;
u8 wake_en : 1; u32 wake_en : 1;
u8 smi : 1; u32 smi : 1;
u8 is_gpio : 1; u32 is_gpio : 1;
u32 sci : 1;
} __attribute__ ((packed)); } __attribute__ ((packed));
struct soc_gpio_config { struct soc_gpio_config {

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@ -17,16 +17,23 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef BAYLEYBAY_THERMAL_H #ifndef BAYTRAIL_HDA_VERB_H
#define BAYLEYBAY_THERMAL_H #define BAYTRAIL_HDA_VERB_H
/* Temperature which OS will shutdown at */ #include <stdint.h>
#define CRITICAL_TEMPERATURE 95
/* Passive cooling policy threshold */ #define HDA_GCAP_REG 0x00
#define PASSIVE_TEMPERATURE 0 #define HDA_GCTL_REG 0x08
#define HDA_GCTL_CRST (1 << 0)
#define HDA_STATESTS_REG 0x0e
#define HDA_IC_REG 0x60
#define HDA_IR_REG 0x64
#define HDA_ICII_REG 0x68
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
/* Temperature which OS will throttle CPU (when using a Fan) */ int hda_codec_detect(u32 base);
#define ACTIVE_TEMPERATURE 80 int hda_codec_write(u32 base, u32 size, const u32 *data);
int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
#endif #endif

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@ -231,6 +231,8 @@ void iosf_ssus_write(int reg, uint32_t val);
# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) # define SB_BIOS_CONFIG_PDM_MODE (1 << 16)
# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) # define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8)
# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) # define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7)
# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3)
# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2)
# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) # define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1)
# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) # define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0)
#define BIOS_RESET_CPL 0x05 #define BIOS_RESET_CPL 0x05
@ -329,4 +331,11 @@ void iosf_ssus_write(int reg, uint32_t val);
#define USHPHY_REE_DAC_CONTROL 0x80b8 #define USHPHY_REE_DAC_CONTROL 0x80b8
#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 #define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000
/*
* LPE Registers
*/
#define LPE_PCICFGCTR1 0x0500
# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0)
# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1)
#endif /* _BAYTRAIL_IOSF_H_ */ #endif /* _BAYTRAIL_IOSF_H_ */

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@ -36,6 +36,7 @@
#define RID_A_STEPPING_START 1 #define RID_A_STEPPING_START 1
#define RID_B_STEPPING_START 5 #define RID_B_STEPPING_START 5
#define RID_C_STEPPING_START 0xe
enum baytrail_stepping { enum baytrail_stepping {
STEP_A0, STEP_A0,
STEP_A1, STEP_A1,
@ -43,6 +44,7 @@ enum baytrail_stepping {
STEP_B1, STEP_B1,
STEP_B2, STEP_B2,
STEP_B3, STEP_B3,
STEP_C0,
}; };
#endif /* _BAYTRAIL_LPC_H_ */ #endif /* _BAYTRAIL_LPC_H_ */

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@ -28,7 +28,7 @@
#ifndef _MRC_WRAPPER_H_ #ifndef _MRC_WRAPPER_H_
#define _MRC_WRAPPER_H_ #define _MRC_WRAPPER_H_
#define MRC_PARAMS_VER 2 #define MRC_PARAMS_VER 3
#define NUM_CHANNELS 2 #define NUM_CHANNELS 2
@ -79,6 +79,7 @@ struct mrc_params {
int txe_size_mb; /* TXE memory size in megabytes. */ int txe_size_mb; /* TXE memory size in megabytes. */
int rmt_enabled; /* Enable RMT training + prints. */ int rmt_enabled; /* Enable RMT training + prints. */
int io_hole_mb; /* Size of IO hole in MiB. */
/* Outputs */ /* Outputs */
void *txe_base_address; void *txe_base_address;

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@ -18,6 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef _BAYTRAIL_NVS_H_
#define _BAYTRAIL_NVS_H_
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
#include <baytrail/device_nvs.h> #include <baytrail/device_nvs.h>
@ -40,7 +43,8 @@ typedef struct {
u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tpmp; /* 0x12 - TPM Present and Enabled */
u8 tlvl; /* 0x13 - Throttle Level */ u8 tlvl; /* 0x13 - Throttle Level */
u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */
u8 rsvd1[11]; u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */
u8 rsvd1[7];
/* Device Config */ /* Device Config */
u8 s5u0; /* 0x20 - Enable USB0 in S5 */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */
@ -70,3 +74,5 @@ typedef struct {
/* Used in SMM to find the ACPI GNVS address */ /* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void); global_nvs_t *smm_get_gnvs(void);
#endif #endif
#endif /* _BAYTRAIL_NVS_H_ */

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@ -200,14 +200,22 @@
#define CORE_GPIO_EN2 (1 << 26) #define CORE_GPIO_EN2 (1 << 26)
#define CORE_GPIO_EN1 (1 << 25) #define CORE_GPIO_EN1 (1 << 25)
#define CORE_GPIO_EN0 (1 << 24) #define CORE_GPIO_EN0 (1 << 24)
#define SUS_GPIO_EN7 (1 << 23) #define SUS_GPIO_EN7_BIT 23
#define SUS_GPIO_EN6 (1 << 22) #define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT)
#define SUS_GPIO_EN5 (1 << 21) #define SUS_GPIO_EN6_BIT 22
#define SUS_GPIO_EN4 (1 << 20) #define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT)
#define SUS_GPIO_EN3 (1 << 19) #define SUS_GPIO_EN5_BIT 21
#define SUS_GPIO_EN2 (1 << 18) #define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT)
#define SUS_GPIO_EN1 (1 << 17) #define SUS_GPIO_EN4_BIT 20
#define SUS_GPIO_EN0 (1 << 16) #define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT)
#define SUS_GPIO_EN3_BIT 19
#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT)
#define SUS_GPIO_EN2_BIT 18
#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT)
#define SUS_GPIO_EN1_BIT 17
#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT)
#define SUS_GPIO_EN0_BIT 16
#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT)
#define PME_B0_EN (1 << 13) #define PME_B0_EN (1 << 13)
#define BATLOW_EN (1 << 10) #define BATLOW_EN (1 << 10)
#define PCI_EXP_EN (1 << 9) #define PCI_EXP_EN (1 << 9)
@ -217,6 +225,8 @@
#define PCIE_WAKE0_EN (1 << 3) #define PCIE_WAKE0_EN (1 << 3)
#define SWGPE_EN (1 << 2) #define SWGPE_EN (1 << 2)
#define HOT_PLUG_EN (1 << 1) #define HOT_PLUG_EN (1 << 1)
#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT
#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x)
#define SMI_EN 0x30 #define SMI_EN 0x30
#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
#define USB_EN (1 << 17) // Legacy USB2 SMI logic #define USB_EN (1 << 17) // Legacy USB2 SMI logic
@ -250,6 +260,8 @@
# define RST_CPU (1 << 2) # define RST_CPU (1 << 2)
# define SYS_RST (1 << 1) # define SYS_RST (1 << 1)
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
/* Track power state from reset to log events. */ /* Track power state from reset to log events. */
struct chipset_power_state { struct chipset_power_state {
uint16_t pm1_sts; uint16_t pm1_sts;
@ -286,4 +298,6 @@ void southcluster_log_state(void);
static inline void southcluster_log_state(void) {} static inline void southcluster_log_state(void) {}
#endif #endif
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _BAYTRAIL_PMC_H_ */ #endif /* _BAYTRAIL_PMC_H_ */

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@ -31,6 +31,13 @@ struct soc_intel_baytrail_config {
uint8_t ide_legacy_combined; uint8_t ide_legacy_combined;
uint8_t clkreq_enable; uint8_t clkreq_enable;
/* VR low power settings -- enable PS2 mode for gfx and core */
int vnn_ps2_enable;
int vcc_ps2_enable;
/* Disable SLP_X stretching after SUS power well loss. */
int disable_slp_x_stretch_sus_fail;
/* USB Port Disable mask */ /* USB Port Disable mask */
uint16_t usb2_port_disable_mask; uint16_t usb2_port_disable_mask;
uint16_t usb3_port_disable_mask; uint16_t usb3_port_disable_mask;

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@ -30,15 +30,15 @@ static const struct reg_script dptf_init_settings[] = {
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029),
/* ratio 10 = 1333mhz for 2.5W fanless */ /* ratio 11 = 1466mhz for mid and entry celeron */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002),
REG_SCRIPT_END, REG_SCRIPT_END,
}; };

View File

@ -42,6 +42,10 @@ static void log_power_and_resets(const struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
} }
if (ps->gen_pmcon1 & RPS) {
elog_add_event(ELOG_TYPE_RTC_RESET);
}
if (ps->tco_sts & SECOND_TO_STS) { if (ps->tco_sts & SECOND_TO_STS) {
elog_add_event(ELOG_TYPE_TCO_RESET); elog_add_event(ELOG_TYPE_TCO_RESET);
} }

View File

@ -142,7 +142,7 @@ static const struct reg_script gfx_init_script[] = {
/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
/* SDP Profile 4 == 0x11940, others 0xcf08 */ /* SDP Profile 4 == 0x11940, others 0xcf08 */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
/* GfxPause */ /* GfxPause */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),

View File

@ -182,13 +182,13 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
/* SMI takes precedence and wake_en implies SCI. */ /* SMI takes precedence and wake_en implies SCI. */
if (sus[i].smi) { if (sus[i].smi) {
route_reg |= ROUTE_SMI << (2 * i); route_reg |= ROUTE_SMI << (2 * i);
} else if (sus[i].wake_en) { } else if (sus[i].sci) {
route_reg |= ROUTE_SCI << (2 * i); route_reg |= ROUTE_SCI << (2 * i);
} }
if (core[i].smi) { if (core[i].smi) {
route_reg |= ROUTE_SMI << (2 * (i + 8)); route_reg |= ROUTE_SMI << (2 * (i + 8));
} else if (core[i].wake_en) { } else if (core[i].sci) {
route_reg |= ROUTE_SCI << (2 * (i + 8)); route_reg |= ROUTE_SCI << (2 * (i + 8));
} }
} }

View File

@ -0,0 +1,121 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <reg_script.h>
#include <baytrail/hda_verb.h>
#include <baytrail/iomap.h>
#include <baytrail/iosf.h>
#include <baytrail/pci_devs.h>
#include <baytrail/ramstage.h>
static const struct reg_script init_ops[] = {
/* Set up VC0 and VC1. */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x24, 0x80000019),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x28, 0x81000022),
/* Enable VCi */
REG_PCI_WRITE32(0x120, 0x81000022),
/* Enable no snoop traffic. */
REG_PCI_OR16(0x78, 1 << 11),
/* Configure HDMI codec connection. */
REG_PCI_OR32(0xc4, 1 << 1),
REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
/* Configure internal settings. */
REG_PCI_OR32(0xc0, 0x7 << 21),
REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
REG_PCI_WRITE32(0xc8, 0x82a30000),
REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
/* Disable docking. */
REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
REG_SCRIPT_END,
};
static const uint32_t hdmi_codec_verb_table[] = {
/* coreboot specific header */
0x80862882, /* vid did for hdmi codec */
0x00000000, /* subsystem id */
0x00000003, /* number of jacks */
/* pin widget 5 - port B */
0x20471c10,
0x20471d00,
0x20471e56,
0x20471f18,
/* pin widget 6 - port C */
0x20571c20,
0x20571d00,
0x20571e56,
0x20571f18,
/* pin widget 7 - port D */
0x20671c30,
0x20671d00,
0x20671e56,
0x20671f58,
};
static void hda_init(device_t dev)
{
struct resource *res;
int codec_mask;
int i;
reg_script_run_on_dev(dev, init_ops);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res == NULL)
return;
codec_mask = hda_codec_detect(res->base);
printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
if (!codec_mask)
return;
for (i = 3; i >= 0; i--) {
if (!((1 << i) & codec_mask))
continue;
hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
hdmi_codec_verb_table);
}
}
static const struct device_operations device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = hda_init,
.enable = NULL,
.scan_bus = NULL,
.ops_pci = &soc_pci_ops,
};
static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = HDA_DEVID,
};

View File

@ -0,0 +1,253 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/io.h>
#include <delay.h>
#include <baytrail/hda_verb.h>
/**
* Set bits in a register and wait for status
*/
static int set_bits(u32 port, u32 mask, u32 val)
{
u32 reg32;
int count;
/* Write (val & mask) to port */
val &= mask;
reg32 = read32(port);
reg32 &= ~mask;
reg32 |= val;
write32(port, reg32);
/* Wait for readback of register to
* match what was just written to it
*/
count = 50;
do {
/* Wait 1ms based on BKDG wait time */
mdelay(1);
reg32 = read32(port);
reg32 &= mask;
} while ((reg32 != val) && --count);
/* Timeout occurred */
if (!count)
return -1;
return 0;
}
/**
* Probe for supported codecs
*/
int hda_codec_detect(u32 base)
{
u8 reg8;
/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
goto no_codec;
/* Write back the value once reset bit is set. */
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
/* Read in Codec location (BAR + 0xe)[2..0]*/
reg8 = read8(base + HDA_STATESTS_REG);
reg8 &= 0x0f;
if (!reg8)
goto no_codec;
return reg8;
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
printk(BIOS_DEBUG, "HDA: No codec!\n");
return 0;
}
/**
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
static int hda_wait_for_ready(u32 base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
}
return -1;
}
/**
* Wait 50usec for the codec to indicate that it accepted
* the previous command. No response would imply that the code
* is non-operative
*/
static int hda_wait_for_valid(u32 base)
{
u32 reg32;
/* Send the verb to the codec */
reg32 = read32(base + HDA_ICII_REG);
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
write32(base + HDA_ICII_REG, reg32);
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
int timeout = 50;
while(timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
return 0;
udelay(1);
}
return -1;
}
/**
* Find a specific entry within a verb table
*
* @verb_table_bytes: verb table size in bytes
* @verb_table_data: verb table data
* @viddid: vendor/device to search for
* @verb_out: pointer to entry within table
*
* Returns size of the entry within the verb table,
* Returns 0 if the entry is not found
*
* The HDA verb table is composed of dwords. A set of 4 dwords is
* grouped together to form a "jack" descriptor.
* Bits 31:28 - Codec Address
* Bits 27:20 - NID
* Bits 19:8 - Verb ID
* Bits 7:0 - Payload
*
* coreboot groups different codec verb tables into a single table
* and prefixes each with a specific header consisting of 3
* dword entries:
* 1 - Codec Vendor/Device ID
* 2 - Subsystem ID
* 3 - Number of jacks (groups of 4 dwords) for this codec
*/
static u32 hda_find_verb(u32 verb_table_bytes,
const u32 *verb_table_data,
u32 viddid, const u32 ** verb)
{
int idx=0;
while (idx < (verb_table_bytes / sizeof(u32))) {
u32 verb_size = 4 * verb_table_data[idx+2]; // in u32
if (verb_table_data[idx] != viddid) {
idx += verb_size + 3; // skip verb + header
continue;
}
*verb = &verb_table_data[idx+3];
return verb_size;
}
/* Not all codecs need to load another verb */
return 0;
}
/**
* Write a supplied verb table
*/
int hda_codec_write(u32 base, u32 size, const u32 *data)
{
int i;
for (i = 0; i < size; i++) {
if (hda_wait_for_ready(base) < 0)
return -1;
write32(base + HDA_IC_REG, data[i]);
if (hda_wait_for_valid(base) < 0)
return -1;
}
return 0;
}
/**
* Initialize codec, then find the verb table and write it
*/
int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;
int rc;
printk(BIOS_DEBUG, "HDA: Initializing codec #%d\n", addr);
if (!verb_size || !verb_data) {
printk(BIOS_DEBUG, "HDA: No verb list!\n");
return -1;
}
/* 1 */
if (hda_wait_for_ready(base) < 0) {
printk(BIOS_DEBUG, " codec not ready.\n");
return -1;
}
reg32 = (addr << 28) | 0x000f0000;
write32(base + HDA_IC_REG, reg32);
if (hda_wait_for_valid(base) < 0) {
printk(BIOS_DEBUG, " codec not valid.\n");
return -1;
}
/* 2 */
reg32 = read32(base + HDA_IR_REG);
printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32);
size = hda_find_verb(verb_size, verb_data, reg32, &verb);
if (!size) {
printk(BIOS_DEBUG, "HDA: No verb table entry found\n");
return -1;
}
/* 3 */
rc = hda_codec_write(base, size, verb);
if (rc < 0)
printk(BIOS_DEBUG, "HDA: verb not loaded\n");
else
printk(BIOS_DEBUG, "HDA: verb loaded.\n");
return rc;
}

View File

@ -18,12 +18,18 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <reg_script.h>
#include <baytrail/iomap.h> #include <baytrail/iomap.h>
#include <baytrail/iosf.h>
#include <baytrail/lpc.h>
#include <baytrail/nvs.h>
#include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h> #include <baytrail/pci_devs.h>
#include <baytrail/pmc.h> #include <baytrail/pmc.h>
#include <baytrail/ramstage.h> #include <baytrail/ramstage.h>
@ -34,8 +40,52 @@
* address. Just take 1MiB @ 512MiB. */ * address. Just take 1MiB @ 512MiB. */
#define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_BASE (512 << 20)
#define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20)
#define FIRMWARE_REG_BASE 0xa8 #define FIRMWARE_PCI_REG_BASE 0xa8
#define FIRMWARE_REG_LENGTH 0xac #define FIRMWARE_PCI_REG_LENGTH 0xac
#define FIRMWARE_REG_BASE_C0 0x144000
#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
{
struct resource *res;
res = find_resource(dev, index);
if (res)
*field = res->base;
}
static void lpe_enable_acpi_mode(device_t dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR32(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
LPE_PCICFGCTR1_PCI_CFG_DIS |
LPE_PCICFGCTR1_ACPI_INT_EN),
REG_SCRIPT_END
};
global_nvs_t *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_ERR, "Unable to locate Global NVS\n");
return;
}
/* Save BAR0, BAR1, and firmware base to ACPI NVS */
assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
/* Device is enabled in ACPI mode */
gnvs->dev.lpe_en = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
}
static void setup_codec_clock(device_t dev) static void setup_codec_clock(device_t dev)
{ {
@ -75,38 +125,54 @@ static void setup_codec_clock(device_t dev)
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
} }
static void lpe_stash_firmware_info(device_t dev)
{
struct resource *res;
struct resource *mmio;
const struct pattrs *pattrs = pattrs_get();
res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
if (res == NULL) {
printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
return;
}
/* Continue using old way of informing firmware address / size. */
pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
/* C0 and later steppings use an offset in the MMIO space. */
if (pattrs->stepping >= STEP_C0) {
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
}
}
static void lpe_init(device_t dev) static void lpe_init(device_t dev)
{ {
struct soc_intel_baytrail_config *config = dev->chip_info;
lpe_stash_firmware_info(dev);
setup_codec_clock(dev); setup_codec_clock(dev);
if (config->lpe_acpi_mode)
lpe_enable_acpi_mode(dev);
} }
static void lpe_read_resources(device_t dev) static void lpe_read_resources(device_t dev)
{ {
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
reserved_ram_resource(dev, FIRMWARE_REG_BASE, reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10); FIRMWARE_PHYS_LENGTH >> 10);
} }
static void lpe_set_resources(device_t dev)
{
struct resource *res;
pci_dev_set_resources(dev);
res = find_resource(dev, FIRMWARE_REG_BASE);
if (res == NULL) {
printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
return;
}
pci_write_config32(dev, FIRMWARE_REG_BASE, res->base);
pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size);
}
static const struct device_operations device_ops = { static const struct device_operations device_ops = {
.read_resources = lpe_read_resources, .read_resources = lpe_read_resources,
.set_resources = lpe_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = lpe_init, .init = lpe_init,
.enable = NULL, .enable = NULL,

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -1,4 +1,4 @@
unsigned microcode[] = { unsigned microcode[] = {
#include "M0C3067_0000031E.h" #include "M0C3067_0000031E.h"
#include "M0C3068_00000808.h" #include "M0C3068_00000809.h"
}; };

View File

@ -358,7 +358,7 @@ void clear_pmc_status(void)
prsts = read32(PMC_BASE_ADDRESS + PRSTS); prsts = read32(PMC_BASE_ADDRESS + PRSTS);
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
/* Clear the status bits. */ /* Clear the status bits. The RPS field is cleared on a 0 write. */
write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
write32(PMC_BASE_ADDRESS + PRSTS, prsts); write32(PMC_BASE_ADDRESS + PRSTS, prsts);
} }

View File

@ -36,6 +36,7 @@
#include <baytrail/nvs.h> #include <baytrail/nvs.h>
#include <baytrail/pattrs.h> #include <baytrail/pattrs.h>
#include <baytrail/pci_devs.h> #include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h> #include <baytrail/ramstage.h>
/* Global PATTRS */ /* Global PATTRS */
@ -71,7 +72,9 @@ static inline void fill_in_msr(msr_t *msr, int idx)
} }
} }
static const char *stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3" }; static const char *stepping_str[] = {
"A0", "A1", "B0", "B1", "B2", "B3", "C0"
};
static void fill_in_pattrs(void) static void fill_in_pattrs(void)
{ {
@ -83,7 +86,10 @@ static void fill_in_pattrs(void)
dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
attrs->revid = pci_read_config8(dev, REVID); attrs->revid = pci_read_config8(dev, REVID);
/* The revision to stepping IDs have two values per metal stepping. */ /* The revision to stepping IDs have two values per metal stepping. */
if (attrs->revid >= RID_B_STEPPING_START) { if (attrs->revid >= RID_C_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
attrs->stepping += STEP_C0;
} else if (attrs->revid >= RID_B_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2;
attrs->stepping += STEP_B0; attrs->stepping += STEP_B0;
} else { } else {
@ -131,6 +137,32 @@ static inline void set_acpi_sleep_type(int val)
#endif #endif
} }
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
uint16_t pm1;
if (!ps)
return;
pm1 = ps->pm1_sts & ps->pm1_en;
/* Scan for first set bit in PM1 */
for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) {
if (pm1 & 1)
break;
pm1 >>= 1;
}
/* If unable to determine then return -1 */
if (gnvs->pm1i >= 16)
gnvs->pm1i = -1;
printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n",
gnvs->pm1i);
}
static void s3_resume_prepare(void) static void s3_resume_prepare(void)
{ {
global_nvs_t *gnvs; global_nvs_t *gnvs;
@ -148,6 +180,8 @@ static void s3_resume_prepare(void)
} }
set_acpi_sleep_type(3); set_acpi_sleep_type(3);
s3_save_acpi_wake_source(gnvs);
} }
void baytrail_init_pre_device(void) void baytrail_init_pre_device(void)

View File

@ -19,11 +19,16 @@
#include <stddef.h> #include <stddef.h>
#include <arch/io.h> #include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <baytrail/iomap.h> #include <baytrail/iomap.h>
#include <baytrail/iosf.h> #include <baytrail/iosf.h>
#include <baytrail/lpc.h>
#include <baytrail/pci_devs.h> #include <baytrail/pci_devs.h>
#include <baytrail/pmc.h> #include <baytrail/pmc.h>
#include <baytrail/romstage.h> #include <baytrail/romstage.h>
#include "../chip.h"
void tco_disable(void) void tco_disable(void)
{ {
@ -38,13 +43,34 @@ void tco_disable(void)
void punit_init(void) void punit_init(void)
{ {
uint32_t reg; uint32_t reg;
uint8_t rid;
const struct device *dev;
const struct soc_intel_baytrail_config *cfg = NULL;
rid = pci_read_config8(IOSF_PCI_DEV, REVID);
dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC));
if (dev)
cfg = dev->chip_info;
reg = iosf_punit_read(SB_BIOS_CONFIG);
/* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */
reg = SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE;
pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); /* Configure VR low power mode for C0 and above. */
reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | if (rid >= RID_C_STEPPING_START && cfg != NULL &&
IOSF_REG(SB_BIOS_CONFIG) | IOSF_BYTE_EN_2; (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) {
pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); printk(BIOS_DEBUG, "Enabling VR PS2 mode: ");
if (cfg->vnn_ps2_enable) {
reg |= SB_BIOS_CONFIG_PS2_EN_VNN;
printk(BIOS_DEBUG, "VNN ");
}
if (cfg->vcc_ps2_enable) {
reg |= SB_BIOS_CONFIG_PS2_EN_VCC;
printk(BIOS_DEBUG, "VCC ");
}
printk(BIOS_DEBUG, "\n");
}
iosf_punit_write(SB_BIOS_CONFIG, reg);
/* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */
reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE;

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@ -121,6 +121,11 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
mp->console_out = &send_to_console; mp->console_out = &send_to_console;
mp->prev_sleep_state = prev_sleep_state; mp->prev_sleep_state = prev_sleep_state;
mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT);
/* Default to 2GiB IO hole. */
if (!mp->io_hole_mb)
mp->io_hole_mb = 2048;
if (recovery_mode_enabled()) { if (recovery_mode_enabled()) {
printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
} else if (!mrc_cache_get_current(&cache)) { } else if (!mrc_cache_get_current(&cache)) {

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@ -20,10 +20,12 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <baytrail/iomap.h> #include <baytrail/iomap.h>
@ -33,6 +35,7 @@
#include <baytrail/pci_devs.h> #include <baytrail/pci_devs.h>
#include <baytrail/pmc.h> #include <baytrail/pmc.h>
#include <baytrail/ramstage.h> #include <baytrail/ramstage.h>
#include "chip.h"
static inline void static inline void
add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
@ -117,13 +120,36 @@ static void sc_read_resources(device_t dev)
sc_add_io_resources(dev); sc_add_io_resources(dev);
} }
static void sc_rtc_init(void)
{
uint32_t gen_pmcon1;
int rtc_fail;
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
if (ps != NULL) {
gen_pmcon1 = ps->gen_pmcon1;
} else {
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
}
rtc_fail = !!(gen_pmcon1 & RPS);
if (rtc_fail) {
printk(BIOS_DEBUG, "RTC failure.\n");
}
rtc_init(rtc_fail);
}
static void sc_init(device_t dev) static void sc_init(device_t dev)
{ {
int i; int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
const unsigned long actl = ILB_BASE_ADDRESS + ACTL; const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
const struct baytrail_irq_route *ir = &global_baytrail_irq_route; const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */ /* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) { for (i = 0; i < NUM_PIRQS; i++) {
@ -136,6 +162,17 @@ static void sc_init(device_t dev)
/* Route SCI to IRQ9 */ /* Route SCI to IRQ9 */
write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9);
sc_rtc_init();
if (config->disable_slp_x_stretch_sus_fail) {
printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
write32(gen_pmcon1,
read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
} else {
write32(gen_pmcon1,
read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
}
} }
/* /*

View File

@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
@ -86,10 +87,6 @@ const struct reg_script xhci_init_script[] = {
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000),
/* BAR + 0x8060[25]=1b */ /* BAR + 0x8060[25]=1b */
REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000),
/* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040),
/* BAR + 0x80e0 toggle bit 24=0 */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0),
/* BAR + 0x80f0[20]=0b */ /* BAR + 0x80f0[20]=0b */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0),
/* BAR + 0x8008[19]=1b (to enable LPM) */ /* BAR + 0x8008[19]=1b (to enable LPM) */
@ -110,6 +107,28 @@ const struct reg_script xhci_init_script[] = {
REG_SCRIPT_END REG_SCRIPT_END
}; };
const struct reg_script xhci_init_boot_script[] = {
/* Setup USB3 phy */
REG_SCRIPT_NEXT(usb3_phy_script),
/* Initialize host controller */
REG_SCRIPT_NEXT(xhci_init_script),
/* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040),
/* BAR + 0x80e0 toggle bit 24=0 */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0),
REG_SCRIPT_END
};
const struct reg_script xhci_init_resume_script[] = {
/* Setup USB3 phy */
REG_SCRIPT_NEXT(usb3_phy_script),
/* Initialize host controller */
REG_SCRIPT_NEXT(xhci_init_script),
/* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040),
REG_SCRIPT_END
};
const struct reg_script xhci_clock_gating_script[] = { const struct reg_script xhci_clock_gating_script[] = {
/* ConfigureXhciClockGating() */ /* ConfigureXhciClockGating() */
/* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */
@ -165,6 +184,9 @@ static void xhci_route_all(device_t dev)
/* Route ports to XHCI controller */ /* Route ports to XHCI controller */
reg_script_run_on_dev(dev, xhci_route_all_script); reg_script_run_on_dev(dev, xhci_route_all_script);
if (acpi_slp_type == 3)
return;
/* Reset enabled USB3 ports */ /* Reset enabled USB3 ports */
port_disabled = pci_read_config32(dev, XHCI_USB3PDO); port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) {
@ -178,10 +200,6 @@ static void xhci_init(device_t dev)
{ {
struct soc_intel_baytrail_config *config = dev->chip_info; struct soc_intel_baytrail_config *config = dev->chip_info;
struct reg_script xhci_hc_init[] = { struct reg_script xhci_hc_init[] = {
/* Setup USB3 phy */
REG_SCRIPT_NEXT(usb3_phy_script),
/* Initialize host controller */
REG_SCRIPT_NEXT(xhci_init_script),
/* Initialize clock gating */ /* Initialize clock gating */
REG_SCRIPT_NEXT(xhci_clock_gating_script), REG_SCRIPT_NEXT(xhci_clock_gating_script),
/* Finalize XHCC1 and XHCC2 */ /* Finalize XHCC1 and XHCC2 */
@ -203,7 +221,13 @@ static void xhci_init(device_t dev)
REG_SCRIPT_END REG_SCRIPT_END
}; };
/* Initialize XHCI controller */ /* Initialize XHCI controller for boot or resume path */
if (acpi_slp_type == 3)
reg_script_run_on_dev(dev, xhci_init_resume_script);
else
reg_script_run_on_dev(dev, xhci_init_boot_script);
/* Finalize Initialization */
reg_script_run_on_dev(dev, xhci_hc_init); reg_script_run_on_dev(dev, xhci_hc_init);
/* Route all ports to XHCI if requested */ /* Route all ports to XHCI if requested */