soc/amd/common/block/spi/fch_spi_util: use [read,write][8,16,32]p

Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8573217d3db5c9d9b042bf1a015366713d508c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67981
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Felix Held 2022-09-29 16:15:28 +02:00
parent 6f9e817bbf
commit 51f60578bb
1 changed files with 7 additions and 7 deletions

View File

@ -2,7 +2,7 @@
#include <amdblocks/lpc.h>
#include <amdblocks/spi.h>
#include <arch/mmio.h>
#include <device/mmio.h>
#include <assert.h>
#include <stdint.h>
@ -27,30 +27,30 @@ uintptr_t spi_get_bar(void)
uint8_t spi_read8(uint8_t reg)
{
return read8((void *)(spi_get_bar() + reg));
return read8p(spi_get_bar() + reg);
}
uint16_t spi_read16(uint8_t reg)
{
return read16((void *)(spi_get_bar() + reg));
return read16p(spi_get_bar() + reg);
}
uint32_t spi_read32(uint8_t reg)
{
return read32((void *)(spi_get_bar() + reg));
return read32p(spi_get_bar() + reg);
}
void spi_write8(uint8_t reg, uint8_t val)
{
write8((void *)(spi_get_bar() + reg), val);
write8p(spi_get_bar() + reg, val);
}
void spi_write16(uint8_t reg, uint16_t val)
{
write16((void *)(spi_get_bar() + reg), val);
write16p(spi_get_bar() + reg, val);
}
void spi_write32(uint8_t reg, uint32_t val)
{
write32((void *)(spi_get_bar() + reg), val);
write32p(spi_get_bar() + reg, val);
}