- Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
parent
49cf5967ce
commit
526855741b
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@ -115,7 +115,7 @@ void lb_strings(struct lb_header *header)
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{ LB_TAG_LINKER, linuxbios_linker, },
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{ LB_TAG_ASSEMBLER, linuxbios_assembler, },
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};
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int i;
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unsigned int i;
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for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
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struct lb_string *rec;
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size_t len;
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@ -35,50 +35,56 @@ static void hlt(void)
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__builtin_hlt();
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}
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static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
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typedef __builtin_msr_t msr_t;
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static msr_t rdmsr(unsigned long index)
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{
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return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
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return __builtin_rdmsr(index);
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}
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static unsigned char pcibios_read_config_byte(
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unsigned char bus, unsigned devfn, unsigned where)
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static void wrmsr(unsigned long index, msr_t msr)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inb(0xCFC + (where & 3));
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__builtin_wrmsr(index, msr.lo, msr.hi);
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}
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static unsigned short pcibios_read_config_word(
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unsigned char bus, unsigned devfn, unsigned where)
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x07) << 8) | \
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((WHERE) & 0xFF))
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static unsigned char pci_read_config8(unsigned addr)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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return inw(0xCFC + (where & 2));
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inb(0xCFC + (addr & 3));
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}
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static unsigned int pcibios_read_config_dword(
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unsigned char bus, unsigned devfn, unsigned where)
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static unsigned short pci_read_config16(unsigned addr)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inw(0xCFC + (addr & 2));
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}
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static unsigned int pci_read_config32(unsigned addr)
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{
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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static void pcibios_write_config_byte(
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unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
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static void pci_write_config8(unsigned addr, unsigned char value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outb(value, 0xCFC + (where & 3));
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outb(value, 0xCFC + (addr & 3));
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}
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static void pcibios_write_config_word(
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unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
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static void pci_write_config16(unsigned addr, unsigned short value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outw(value, 0xCFC + (where & 2));
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outw(value, 0xCFC + (addr & 2));
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}
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static void pcibios_write_config_dword(
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unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
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static void pci_write_config32(unsigned addr, unsigned int value)
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{
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outl(config_cmd(bus, devfn, where), 0xCF8);
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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@ -1,6 +1,12 @@
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#ifndef I386_STDINT_H
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#define I386_STDINT_H
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#if defined(__GNUC__)
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#define __HAVE_LONG_LONG__ 1
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#else
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#define __HAVE_LONG_LONG__ 0
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#endif
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/* Exact integral types */
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typedef unsigned char uint8_t;
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typedef signed char int8_t;
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@ -11,8 +17,10 @@ typedef signed short int16_t;
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typedef unsigned int uint32_t;
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typedef signed int int32_t;
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#if __HAVE_LONG_LONG__
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typedef unsigned long long uint64_t;
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typedef signed long long int64_t;
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#endif
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/* Small types */
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typedef unsigned char uint_least8_t;
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@ -24,8 +32,10 @@ typedef signed short int_least16_t;
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typedef unsigned int uint_least32_t;
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typedef signed int int_least32_t;
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#if __HAVE_LONG_LONG__
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typedef unsigned long long uint_least64_t;
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typedef signed long long int_least64_t;
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#endif
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/* Fast Types */
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typedef unsigned char uint_fast8_t;
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@ -37,16 +47,25 @@ typedef signed int int_fast16_t;
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typedef unsigned int uint_fast32_t;
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typedef signed int int_fast32_t;
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#if __HAVE_LONG_LONG__
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typedef unsigned long long uint_fast64_t;
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typedef signed long long int_fast64_t;
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#endif
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/* Types for `void *' pointers. */
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typedef int intptr_t;
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typedef unsigned int uintptr_t;
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/* Largest integral types */
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#if __HAVE_LONG_LONG__
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typedef long long int intmax_t;
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typedef unsigned long long uintmax_t;
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#else
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typedef long int intmax_t;
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typedef unsigned long int uintmax_t;
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#endif
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#undef __HAVE_LONG_LONG__
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#endif /* I386_STDINT_H */
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@ -22,11 +22,21 @@ static void __console_tx_char(int loglevel, unsigned char byte)
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}
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}
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static void __console_tx_hex8(int loglevel, unsigned char byte)
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static void __console_tx_hex8(int loglevel, unsigned char value)
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{
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if (ASM_CONSOLE_LOGLEVEL > loglevel) {
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__console_tx_nibble(byte >> 4U);
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__console_tx_nibble(byte & 0x0fU);
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__console_tx_nibble((value >> 4U) & 0x0fU);
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__console_tx_nibble(value & 0x0fU);
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}
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}
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static void __console_tx_hex16(int loglevel, unsigned short value)
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{
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if (ASM_CONSOLE_LOGLEVEL > loglevel) {
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__console_tx_nibble((value >> 12U) & 0x0fU);
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__console_tx_nibble((value >> 8U) & 0x0fU);
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__console_tx_nibble((value >> 4U) & 0x0fU);
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__console_tx_nibble(value & 0x0fU);
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}
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}
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@ -56,46 +66,55 @@ static void __console_tx_string(int loglevel, const char *str)
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static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); }
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static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); }
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static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); }
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static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); }
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static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); }
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static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); }
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static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); }
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static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); }
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static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); }
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static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); }
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static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); }
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static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); }
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static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); }
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static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); }
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static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); }
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static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); }
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static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); }
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static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); }
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static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); }
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static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); }
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static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); }
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static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); }
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static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); }
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static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); }
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static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); }
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static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); }
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static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); }
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static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); }
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static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); }
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static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); }
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static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); }
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static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); }
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static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); }
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static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); }
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static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); }
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static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); }
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static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); }
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static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); }
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static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); }
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static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); }
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static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); }
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static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); }
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static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); }
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static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); }
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static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
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@ -161,7 +161,7 @@ void hardwaremain(int boot_complete)
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#endif
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#if 1
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// pick how to scan the bus. This is first so we can get at memory size.
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/* pick how to scan the bus. This is first so we can get at memory size. */
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printk_info("Finding PCI configuration type.\n");
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pci_set_method();
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post_code(0x5f);
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@ -170,13 +170,15 @@ void hardwaremain(int boot_complete)
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#endif
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dev_enumerate();
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post_code(0x66);
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// Now do the real bus
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// we round the total ram up a lot for thing like the SISFB, which
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// shares high memory with the CPU.
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/* Now do the real bus.
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* We round the total ram up a lot for thing like the SISFB, which
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* shares high memory with the CPU.
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*/
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dev_configure();
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post_code(0x88);
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dev_enable();
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dev_initialize();
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post_code(0x89);
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#endif
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@ -46,12 +46,12 @@ set_var_mtrr:
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wrmsr
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#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
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/* enable write protect caching so we can do execute in place
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/* enable write back cachine so we can do execute in place
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* on the flash rom.
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*/
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movl $0x202, %ecx
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xorl %edx, %edx
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movl $(XIP_ROM_BASE | 0x005), %eax
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movl $(XIP_ROM_BASE | 0x006), %eax
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wrmsr
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movl $0x203, %ecx
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@ -1,7 +1,3 @@
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <console/console.h>
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#include <cpu/p5/cpuid.h>
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#ifdef i586
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@ -25,10 +25,6 @@
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* $Id$
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*/
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <console/console.h>
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#include <mem.h>
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#include <cpu/p6/msr.h>
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@ -128,8 +124,6 @@ static void intel_set_var_mtrr(unsigned int reg, unsigned long basek, unsigned l
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/* setting variable mtrr, comes from linux kernel source */
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void set_var_mtrr(unsigned int reg, unsigned long base, unsigned long size, unsigned char type)
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{
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unsigned int tmp;
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if (reg >= 8)
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return;
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@ -537,7 +537,7 @@ unsigned int pci_scan_bus(struct device *bus, unsigned int max)
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/* probe all devices on this bus with some optimization for non-existance and
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single funcion devices */
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for (devfn = 0; devfn < 0xff; devfn++) {
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for (devfn = 0; devfn <= 0xff; devfn++) {
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struct device dummy;
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uint32_t id, class;
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uint8_t cmd, tmp, hdr_type;
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@ -17,267 +17,7 @@
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#ifndef PCI_H
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#define PCI_H
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/*
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* Under PCI, each device has 256 bytes of configuration address space,
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* of which the first 64 bytes are standardized as follows:
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*/
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#define PCI_VENDOR_ID 0x00 /* 16 bits */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND 0x04 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
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#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
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#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
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#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
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#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
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#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
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#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
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#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
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#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
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#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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#define PCI_STATUS_DEVSEL_FAST 0x000
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#define PCI_STATUS_DEVSEL_MEDIUM 0x200
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#define PCI_STATUS_DEVSEL_SLOW 0x400
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#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
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#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
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#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
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#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
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#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
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revision */
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#define PCI_REVISION_ID 0x08 /* Revision ID */
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#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
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#define PCI_CLASS_DEVICE 0x0a /* Device class */
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#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
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#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
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#define PCI_HEADER_TYPE 0x0e /* 8 bits */
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#define PCI_HEADER_TYPE_NORMAL 0
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#define PCI_HEADER_TYPE_BRIDGE 1
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#define PCI_HEADER_TYPE_CARDBUS 2
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#define PCI_BIST 0x0f /* 8 bits */
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#define PCI_BIST_CODE_MASK 0x0f /* Return result */
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#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
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#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
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/*
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* Base addresses specify locations in memory or I/O space.
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* Decoded size can be determined by writing a value of
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* 0xffffffff to the register, and reading it back. Only
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* 1 bits are decoded.
|
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*/
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#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
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#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
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#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
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#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
|
||||
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
|
||||
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
|
||||
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
|
||||
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
|
||||
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
|
||||
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
|
||||
#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
|
||||
/* bit 1 is reserved if address_space = 1 */
|
||||
|
||||
/* Header type 0 (normal devices) */
|
||||
#define PCI_CARDBUS_CIS 0x28
|
||||
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
|
||||
#define PCI_SUBSYSTEM_ID 0x2e
|
||||
#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
|
||||
#define PCI_ROM_ADDRESS_ENABLE 0x01
|
||||
#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
|
||||
|
||||
#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
|
||||
|
||||
/* 0x35-0x3b are reserved */
|
||||
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
|
||||
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
|
||||
#define PCI_MIN_GNT 0x3e /* 8 bits */
|
||||
#define PCI_MAX_LAT 0x3f /* 8 bits */
|
||||
|
||||
/* Header type 1 (PCI-to-PCI bridges) */
|
||||
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
|
||||
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
|
||||
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
|
||||
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
|
||||
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
|
||||
#define PCI_IO_LIMIT 0x1d
|
||||
#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
|
||||
#define PCI_IO_RANGE_TYPE_16 0x00
|
||||
#define PCI_IO_RANGE_TYPE_32 0x01
|
||||
#define PCI_IO_RANGE_MASK ~0x0f
|
||||
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
|
||||
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
|
||||
#define PCI_MEMORY_LIMIT 0x22
|
||||
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
|
||||
#define PCI_MEMORY_RANGE_MASK ~0x0f
|
||||
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
|
||||
#define PCI_PREF_MEMORY_LIMIT 0x26
|
||||
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
|
||||
#define PCI_PREF_RANGE_TYPE_32 0x00
|
||||
#define PCI_PREF_RANGE_TYPE_64 0x01
|
||||
#define PCI_PREF_RANGE_MASK ~0x0f
|
||||
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
|
||||
#define PCI_PREF_LIMIT_UPPER32 0x2c
|
||||
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
|
||||
#define PCI_IO_LIMIT_UPPER16 0x32
|
||||
/* 0x34 same as for htype 0 */
|
||||
/* 0x35-0x3b is reserved */
|
||||
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
|
||||
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
|
||||
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
|
||||
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
|
||||
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
|
||||
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
|
||||
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
|
||||
|
||||
/* Header type 2 (CardBus bridges) */
|
||||
#define PCI_CB_CAPABILITY_LIST 0x14
|
||||
/* 0x15 reserved */
|
||||
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
|
||||
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
|
||||
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
|
||||
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
|
||||
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
|
||||
#define PCI_CB_MEMORY_BASE_0 0x1c
|
||||
#define PCI_CB_MEMORY_LIMIT_0 0x20
|
||||
#define PCI_CB_MEMORY_BASE_1 0x24
|
||||
#define PCI_CB_MEMORY_LIMIT_1 0x28
|
||||
#define PCI_CB_IO_BASE_0 0x2c
|
||||
#define PCI_CB_IO_BASE_0_HI 0x2e
|
||||
#define PCI_CB_IO_LIMIT_0 0x30
|
||||
#define PCI_CB_IO_LIMIT_0_HI 0x32
|
||||
#define PCI_CB_IO_BASE_1 0x34
|
||||
#define PCI_CB_IO_BASE_1_HI 0x36
|
||||
#define PCI_CB_IO_LIMIT_1 0x38
|
||||
#define PCI_CB_IO_LIMIT_1_HI 0x3a
|
||||
#define PCI_CB_IO_RANGE_MASK ~0x03
|
||||
/* 0x3c-0x3d are same as for htype 0 */
|
||||
#define PCI_CB_BRIDGE_CONTROL 0x3e
|
||||
#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
|
||||
#define PCI_CB_BRIDGE_CTL_SERR 0x02
|
||||
#define PCI_CB_BRIDGE_CTL_ISA 0x04
|
||||
#define PCI_CB_BRIDGE_CTL_VGA 0x08
|
||||
#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
|
||||
#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
|
||||
#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
|
||||
#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
|
||||
#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
|
||||
#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
|
||||
#define PCI_CB_SUBSYSTEM_ID 0x42
|
||||
#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
|
||||
/* 0x48-0x7f reserved */
|
||||
|
||||
/* Capability lists */
|
||||
|
||||
#define PCI_CAP_LIST_ID 0 /* Capability ID */
|
||||
#define PCI_CAP_ID_PM 0x01 /* Power Management */
|
||||
#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
|
||||
#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
|
||||
#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
|
||||
#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
|
||||
#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
|
||||
#define PCI_CAP_ID_HT 0x08
|
||||
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
|
||||
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
|
||||
#define PCI_CAP_SIZEOF 4
|
||||
|
||||
/* Power Management Registers */
|
||||
|
||||
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
|
||||
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
|
||||
#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
|
||||
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
|
||||
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
|
||||
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
|
||||
#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
|
||||
#define PCI_PM_CTRL 4 /* PM control and status register */
|
||||
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
|
||||
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
|
||||
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
|
||||
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
|
||||
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
|
||||
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
|
||||
#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
|
||||
#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
|
||||
#define PCI_PM_DATA_REGISTER 7 /* (??) */
|
||||
#define PCI_PM_SIZEOF 8
|
||||
|
||||
/* AGP registers */
|
||||
|
||||
#define PCI_AGP_VERSION 2 /* BCD version number */
|
||||
#define PCI_AGP_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_AGP_STATUS 4 /* Status register */
|
||||
#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
|
||||
#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
|
||||
#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
|
||||
#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
|
||||
#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
|
||||
#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
|
||||
#define PCI_AGP_COMMAND 8 /* Control register */
|
||||
#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
|
||||
#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
|
||||
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
|
||||
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
|
||||
#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
|
||||
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
|
||||
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
|
||||
#define PCI_AGP_SIZEOF 12
|
||||
|
||||
/* Slot Identification */
|
||||
|
||||
#define PCI_SID_ESR 2 /* Expansion Slot Register */
|
||||
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
|
||||
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
|
||||
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
|
||||
|
||||
/* Message Signalled Interrupts registers */
|
||||
|
||||
#define PCI_MSI_FLAGS 2 /* Various flags */
|
||||
#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
|
||||
#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
|
||||
#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
|
||||
#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
|
||||
#define PCI_MSI_RFU 3 /* Rest of capability flags */
|
||||
#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
|
||||
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
|
||||
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
|
||||
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
|
||||
|
||||
/*
|
||||
* The PCI interface treats multi-function devices as independent
|
||||
* devices. The slot/function address of each device is encoded
|
||||
* in a single byte as follows:
|
||||
*
|
||||
* 7:3 = slot
|
||||
* 2:0 = function
|
||||
*/
|
||||
#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
|
||||
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
|
||||
#define PCI_FUNC(devfn) ((devfn) & 0x07)
|
||||
#define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8)
|
||||
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <device/resource.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
|
|
|||
|
|
@ -402,6 +402,15 @@
|
|||
#define PCI_DEVICE_ID_AMD_VIPER_7448 0x7448
|
||||
#define PCI_DEVICE_ID_AMD_VIPER_7449 0x7449
|
||||
|
||||
#define PCI_DEVICE_ID_AMD_8151_SYSCTRL 0x7454
|
||||
#define PCI_DEVICE_ID_AMD_8151_AGP 0x7455
|
||||
#define PCI_DEVICE_ID_AMD_8111_PCI 0x7460
|
||||
#define PCI_DEVICE_ID_AMD_8111_USB 0x7464
|
||||
#define PCI_DEVICE_ID_AMD_8111_ISA 0x7468
|
||||
#define PCI_DEVICE_ID_AMD_8111_IDE 0x7469
|
||||
#define PCI_DEVICE_ID_AMD_8111_SMB 0x746a
|
||||
#define PCI_DEVICE_ID_AMD_8111_ACPI 0x746b
|
||||
|
||||
#define PCI_VENDOR_ID_TRIDENT 0x1023
|
||||
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000
|
||||
#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX 0x2001
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -9,129 +9,3 @@ unsigned long initial_apicid[MAX_CPUS] =
|
|||
{
|
||||
0
|
||||
};
|
||||
|
||||
void
|
||||
mainboard_fixup(void)
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
final_mainboard_fixup(void)
|
||||
{
|
||||
#if 0
|
||||
// void final_southbridge_fixup(void);
|
||||
// void final_superio_fixup(void);
|
||||
|
||||
printk_info("AMD Solo initializing...");
|
||||
|
||||
// final_southbridge_fixup();
|
||||
|
||||
//#ifndef USE_NEW_SUPERIO_INTERFACE
|
||||
//final_superio_fixup();
|
||||
//#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
struct ioapicreg {
|
||||
unsigned int reg;
|
||||
unsigned int value_low, value_high;
|
||||
};
|
||||
static struct ioapicreg ioapicregvalues[] = {
|
||||
#define ALL (0xff << 24)
|
||||
#define NONE (0)
|
||||
#define DISABLED (1 << 16)
|
||||
#define ENABLED (0 << 16)
|
||||
#define TRIGGER_EDGE (0 << 15)
|
||||
#define TRIGGER_LEVEL (1 << 15)
|
||||
#define POLARITY_HIGH (0 << 13)
|
||||
#define POLARITY_LOW (1 << 13)
|
||||
#define PHYSICAL_DEST (0 << 11)
|
||||
#define LOGICAL_DEST (1 << 11)
|
||||
#define ExtINT (7 << 8)
|
||||
#define NMI (4 << 8)
|
||||
#define SMI (2 << 8)
|
||||
#define INT (1 << 8)
|
||||
/* mask, trigger, polarity, destination, delivery, vector */
|
||||
{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
|
||||
{0x01, DISABLED, NONE},
|
||||
{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
|
||||
{0x03, DISABLED, NONE},
|
||||
{0x04, DISABLED, NONE},
|
||||
{0x05, DISABLED, NONE},
|
||||
{0x06, DISABLED, NONE},
|
||||
{0x07, DISABLED, NONE},
|
||||
{0x08, DISABLED, NONE},
|
||||
{0x09, DISABLED, NONE},
|
||||
{0x0a, DISABLED, NONE},
|
||||
{0x0b, DISABLED, NONE},
|
||||
{0x0c, DISABLED, NONE},
|
||||
{0x0d, DISABLED, NONE},
|
||||
{0x0e, DISABLED, NONE},
|
||||
{0x0f, DISABLED, NONE},
|
||||
{0x10, DISABLED, NONE},
|
||||
{0x11, DISABLED, NONE},
|
||||
{0x12, DISABLED, NONE},
|
||||
{0x13, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x15, DISABLED, NONE},
|
||||
{0x16, DISABLED, NONE},
|
||||
{0x17, DISABLED, NONE},
|
||||
{0x18, DISABLED, NONE},
|
||||
{0x19, DISABLED, NONE},
|
||||
{0x20, DISABLED, NONE},
|
||||
{0x21, DISABLED, NONE},
|
||||
{0x22, DISABLED, NONE},
|
||||
{0x23, DISABLED, NONE},
|
||||
};
|
||||
|
||||
static void setup_ioapic(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long value_low, value_high;
|
||||
unsigned long ioapic_base = 0xfec00000;
|
||||
volatile unsigned long *l;
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
l = (unsigned long *) ioapic_base;
|
||||
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
|
||||
i++, a++) {
|
||||
l[0] = (a->reg * 2) + 0x10;
|
||||
l[4] = a->value_low;
|
||||
value_low = l[4];
|
||||
l[0] = (a->reg *2) + 0x11;
|
||||
l[4] = a->value_high;
|
||||
value_high = l[4];
|
||||
if ((i==0) && (value_low == 0xffffffff)) {
|
||||
printk_warning("IO APIC not responding.\n");
|
||||
return;
|
||||
}
|
||||
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||
a->reg, a->value_low, a->value_high);
|
||||
}
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
printk_debug("lpc_init\n");
|
||||
#if 0
|
||||
pci_read_config_byte(dev, 0x4B, &byte);
|
||||
byte |= 1;
|
||||
pci_write_config_byte(dev, 0x4B, byte);
|
||||
setup_ioapic();
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = 0x7468,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
static void write_phys(unsigned long addr, unsigned long value)
|
||||
{
|
||||
unsigned long *ptr;
|
||||
volatile unsigned long *ptr;
|
||||
ptr = (void *)addr;
|
||||
*ptr = value;
|
||||
}
|
||||
|
||||
static unsigned long read_phys(unsigned long addr)
|
||||
{
|
||||
unsigned long *ptr;
|
||||
volatile unsigned long *ptr;
|
||||
ptr = (void *)addr;
|
||||
return *ptr;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
static void acpi_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
uint16_t word;
|
||||
|
||||
#if 0
|
||||
printk_debug("ACPI: disabling NMI watchdog.. ");
|
||||
pci_read_config_byte(dev, 0x49, &byte);
|
||||
pci_write_config_byte(dev, 0x49, byte | (1<<2));
|
||||
|
||||
|
||||
pci_read_config_byte(dev, 0x41, &byte);
|
||||
pci_write_config_byte(dev, 0x41, byte | (1<<6)|(1<<2));
|
||||
|
||||
/* added from sourceforge */
|
||||
pci_read_config_byte(dev, 0x48, &byte);
|
||||
pci_write_config_byte(dev, 0x48, byte | (1<<3));
|
||||
|
||||
printk_debug("done.\n");
|
||||
|
||||
|
||||
printk_debug("ACPI: Routing IRQ 12 to PS2 port.. ");
|
||||
pci_read_config_word(dev, 0x46, &word);
|
||||
pci_write_config_word(dev, 0x46, word | (1<<9));
|
||||
printk_debug("done.\n");
|
||||
|
||||
|
||||
printk_debug("ACPI: setting PM class code.. ");
|
||||
pci_write_config_dword(dev, 0x60, 0x06800000);
|
||||
printk_debug("done.\n");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations acpi_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = acpi_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver acpi_driver __pci_driver = {
|
||||
.ops = &acpi_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_8111_ACPI,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
|
||||
/* Enable ide devices so the linux ide driver will work */
|
||||
uint16_t word;
|
||||
int enable_a=1, enable_b=1;
|
||||
|
||||
|
||||
printk_debug("ide_init\n");
|
||||
|
||||
pci_read_config_word(dev, 0x40, &word);
|
||||
/* Ensure prefetch is disabled */
|
||||
word &= ~((1 << 15) | (1 << 13));
|
||||
if (enable_b) {
|
||||
/* Enable secondary ide interface */
|
||||
word |= (1<<0);
|
||||
printk_debug("IDE1 ");
|
||||
}
|
||||
if (enable_a) {
|
||||
/* Enable primary ide interface */
|
||||
word |= (1<<1);
|
||||
printk_debug("IDE0 ");
|
||||
}
|
||||
|
||||
word |= (1<<12);
|
||||
word |= (1<<14);
|
||||
|
||||
pci_write_config_word(dev, 0x40, word);
|
||||
|
||||
word = 0x0f;
|
||||
pci_write_config_word(dev, 0x42, word);
|
||||
|
||||
/* The AMD768 has a bug where the BM DMA address must be
|
||||
* 256 byte aligned while it is only 16 bytes long.
|
||||
* Hard code this to a valid address below 0x1000
|
||||
* where automatic port address assignment starts.
|
||||
* FIXME: I assume the 8111 does the same thing. We should
|
||||
* clarify. stepan@suse.de
|
||||
*/
|
||||
pci_write_config_dword(dev, 0x20, 0xf01);
|
||||
|
||||
pci_write_config_dword(dev, 0x48, 0x205e5e5e);
|
||||
word = 0x06a;
|
||||
pci_write_config_word(dev, 0x4c, word);
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = ide_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver ide_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_8111_IDE,
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,130 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
|
||||
struct ioapicreg {
|
||||
unsigned int reg;
|
||||
unsigned int value_low, value_high;
|
||||
};
|
||||
|
||||
static struct ioapicreg ioapicregvalues[] = {
|
||||
#define ALL (0xff << 24)
|
||||
#define NONE (0)
|
||||
#define DISABLED (1 << 16)
|
||||
#define ENABLED (0 << 16)
|
||||
#define TRIGGER_EDGE (0 << 15)
|
||||
#define TRIGGER_LEVEL (1 << 15)
|
||||
#define POLARITY_HIGH (0 << 13)
|
||||
#define POLARITY_LOW (1 << 13)
|
||||
#define PHYSICAL_DEST (0 << 11)
|
||||
#define LOGICAL_DEST (1 << 11)
|
||||
#define ExtINT (7 << 8)
|
||||
#define NMI (4 << 8)
|
||||
#define SMI (2 << 8)
|
||||
#define INT (1 << 8)
|
||||
/* mask, trigger, polarity, destination, delivery, vector */
|
||||
{0x00, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT | 0, 0},
|
||||
{0x01, DISABLED, NONE},
|
||||
{0x02, ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | INT | 0, 0},
|
||||
{0x03, DISABLED, NONE},
|
||||
{0x04, DISABLED, NONE},
|
||||
{0x05, DISABLED, NONE},
|
||||
{0x06, DISABLED, NONE},
|
||||
{0x07, DISABLED, NONE},
|
||||
{0x08, DISABLED, NONE},
|
||||
{0x09, DISABLED, NONE},
|
||||
{0x0a, DISABLED, NONE},
|
||||
{0x0b, DISABLED, NONE},
|
||||
{0x0c, DISABLED, NONE},
|
||||
{0x0d, DISABLED, NONE},
|
||||
{0x0e, DISABLED, NONE},
|
||||
{0x0f, DISABLED, NONE},
|
||||
{0x10, DISABLED, NONE},
|
||||
{0x11, DISABLED, NONE},
|
||||
{0x12, DISABLED, NONE},
|
||||
{0x13, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x14, DISABLED, NONE},
|
||||
{0x15, DISABLED, NONE},
|
||||
{0x16, DISABLED, NONE},
|
||||
{0x17, DISABLED, NONE},
|
||||
{0x18, DISABLED, NONE},
|
||||
{0x19, DISABLED, NONE},
|
||||
{0x20, DISABLED, NONE},
|
||||
{0x21, DISABLED, NONE},
|
||||
{0x22, DISABLED, NONE},
|
||||
{0x23, DISABLED, NONE},
|
||||
};
|
||||
|
||||
static void setup_ioapic(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long value_low, value_high;
|
||||
unsigned long ioapic_base = 0xfec00000;
|
||||
volatile unsigned long *l;
|
||||
struct ioapicreg *a = ioapicregvalues;
|
||||
|
||||
l = (unsigned long *) ioapic_base;
|
||||
for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
|
||||
i++, a++) {
|
||||
l[0] = (a->reg * 2) + 0x10;
|
||||
l[4] = a->value_low;
|
||||
value_low = l[4];
|
||||
l[0] = (a->reg *2) + 0x11;
|
||||
l[4] = a->value_high;
|
||||
value_high = l[4];
|
||||
if ((i==0) && (value_low == 0xffffffff)) {
|
||||
printk_warning("IO APIC not responding.\n");
|
||||
return;
|
||||
}
|
||||
printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n",
|
||||
a->reg, a->value_low, a->value_high);
|
||||
}
|
||||
}
|
||||
|
||||
static void lpc_init(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
int pwr_on=-1;
|
||||
|
||||
printk_debug("lpc_init\n");
|
||||
|
||||
#if 0
|
||||
/* IO APIC initialization */
|
||||
pci_read_config_byte(dev, 0x4B, &byte);
|
||||
byte |= 1;
|
||||
pci_write_config_byte(dev, 0x4B, byte);
|
||||
setup_ioapic();
|
||||
#endif
|
||||
|
||||
/* posted memory write enable */
|
||||
pci_read_config_byte(dev, 0x46, &byte);
|
||||
pci_write_config_byte(dev, 0x46, byte | (1<<0));
|
||||
|
||||
/* power after power fail */
|
||||
pci_read_config_byte(dev, 0x43, &byte);
|
||||
if (pwr_on) {
|
||||
byte &= ~(1<<6);
|
||||
} else {
|
||||
byte |= (1<<6);
|
||||
}
|
||||
pci_write_config_byte(dev, 0x43, byte);
|
||||
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations lpc_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = lpc_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver lpc_driver __pci_driver = {
|
||||
.ops = &lpc_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_8111_ISA,
|
||||
};
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
#include <smbus.h>
|
||||
#include <pci.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#define PM_BUS 0
|
||||
#define PM_DEVFN (AMD8111_DEVFN+3)
|
||||
|
||||
#define SMBUS_IO_BASE 0x1000
|
||||
#define SMBHSTSTAT 0
|
||||
#define SMBHSTCTL 2
|
||||
#define SMBHSTCMD 3
|
||||
#define SMBHSTADD 4
|
||||
#define SMBHSTDAT0 5
|
||||
#define SMBHSTDAT1 6
|
||||
#define SMBBLKDAT 7
|
||||
|
||||
void smbus_enable(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
#if 0
|
||||
/* iobase addr */
|
||||
pcibios_write_config_dword(PM_BUS, PM_DEVFN, 0x90, SMBUS_IO_BASE | 1);
|
||||
/* smbus enable */
|
||||
pcibios_write_config_byte(PM_BUS, PM_DEVFN, 0xd2, (0x4 << 1) | 1);
|
||||
/* iospace enable */
|
||||
pcibios_write_config_word(PM_BUS, PM_DEVFN, 0x4, 1);
|
||||
#endif
|
||||
/* Set PMIOEN, leaving default address 0xDD00 in 0x58 */
|
||||
byte=pcibios_read_config_byte(0,PCI_DEVFN(0x7,3), 0x41);
|
||||
pcibios_write_config_byte(0,PCI_DEVFN(0x7,3), byte | 0x80 );
|
||||
|
||||
|
||||
/* cont reading 207 */
|
||||
}
|
||||
|
||||
void smbus_setup(void)
|
||||
{
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
|
||||
static void smbus_wait_until_ready(void)
|
||||
{
|
||||
while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
|
||||
/* nop */
|
||||
}
|
||||
}
|
||||
|
||||
static void smbus_wait_until_done(void)
|
||||
{
|
||||
unsigned char byte;
|
||||
do {
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
while((byte &1) == 1);
|
||||
while( (byte & ~1) == 0) {
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
}
|
||||
}
|
||||
|
||||
int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
|
||||
{
|
||||
unsigned char host_status_register;
|
||||
unsigned char byte;
|
||||
|
||||
smbus_wait_until_ready();
|
||||
|
||||
/* setup transaction */
|
||||
/* disable interrupts */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
/* set the device I'm talking too */
|
||||
outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
|
||||
/* set the command/address... */
|
||||
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
|
||||
/* set up for a byte data read */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* clear any lingering errors, so the transaction will run */
|
||||
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* clear the data byte...*/
|
||||
outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
/* start the command */
|
||||
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
|
||||
|
||||
/* poll for transaction completion */
|
||||
smbus_wait_until_done();
|
||||
|
||||
host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
|
||||
|
||||
/* read results of transaction */
|
||||
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
|
||||
|
||||
*result = byte;
|
||||
return host_status_register != 0x02;
|
||||
}
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
static void usb_init(struct device *dev)
|
||||
{
|
||||
uint32_t cmd;
|
||||
|
||||
printk_debug("USB: Setting up controller.. ");
|
||||
pci_read_config_dword(dev, PCI_COMMAND, &cmd);
|
||||
pci_write_config_dword(dev, PCI_COMMAND,
|
||||
cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
|
||||
|
||||
|
||||
printk_debug("done.\n");
|
||||
|
||||
}
|
||||
|
||||
static struct device_operations usb_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.init = usb_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver usb_driver __pci_driver = {
|
||||
.ops = &usb_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_8111_USB,
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue