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revert the faulty part of r5252 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-03-17 22:08:51 +00:00 committed by Stefan Reinauer
parent 0719047005
commit 527aedc17b
1 changed files with 27 additions and 0 deletions
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27
src/southbridge/intel/i82801dx/i82801dx_lpc.c
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@ -177,6 +177,30 @@ static void i82801dx_lpc_decode_en(device_t dev)
pci_write_config16(dev, LPC_EN, 0x300F); pci_write_config16(dev, LPC_EN, 0x300F);
} }
/* ICH4 does not mention HPET in the docs, but
* all ICH3 and ICH4 do have HPETs built in.
*/
static void enable_hpet(struct device *dev)
{
u32 reg32;
u32 code = (0 & 0x3);
reg32 = pci_read_config32(dev, GEN_CNTL);
reg32 |= (1 << 17); /* Enable HPET. */
/*
* Bits [16:15] Memory Address Range
* 00 FED0_0000h - FED0_03FFh
* 01 FED0_1000h - FED0_13FFh
* 10 FED0_2000h - FED0_23FFh
* 11 FED0_3000h - FED0_33FFh
*/
reg32 &= ~(3 << 15); /* Clear it */
reg32 |= (code << 15);
pci_write_config32(dev, GEN_CNTL, reg32);
printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12));
}
static void lpc_init(struct device *dev) static void lpc_init(struct device *dev)
{ {
/* Set the value for PCI command register. */ /* Set the value for PCI command register. */
@ -207,6 +231,9 @@ static void lpc_init(struct device *dev)
/* Setup decode ports and LPC I/F enables. */ /* Setup decode ports and LPC I/F enables. */
i82801dx_lpc_decode_en(dev); i82801dx_lpc_decode_en(dev);
/* Initialize the High Precision Event Timers */
enable_hpet(dev);
} }
static void i82801dx_lpc_read_resources(device_t dev) static void i82801dx_lpc_read_resources(device_t dev)