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remove old config files, adopt to new config method. fix resource map (?) 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2003-09-09 13:30:58 +00:00
parent dad60489d5
commit 5282cd0875
7 changed files with 387 additions and 144 deletions
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381
src/mainboard/amd/quartet/Config.lb
View File

@ -1,36 +1,180 @@
uses HAVE_MP_TABLE uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE uses USE_FALLBACK_IMAGE
# uses MAINBOARD
# uses ARCH
uses FALLBACK_SIZE
uses ROM_SIZE
uses ROM_SECTION_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
uses CONFIG_ROM_STREAM_START
uses PAYLOAD_SIZE
uses _ROMBASE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
### ###
### Set all of the defaults for an x86 architecture ### Build options
### ###
#
# ##
## Build code for the fallback boot
##
option HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from linuxBIOS
##
option HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=7
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
option HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
option HAVE_OPTION_TABLE=1
##
## Build code for SMP support
## Only worry about 2 micro processors
##
option CONFIG_SMP=1
option CONFIG_MAX_CPUS=4
##
## Build code to setup a generic IOAPIC
##
option CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
option MAINBOARD_PART_NUMBER="QUARTET"
option MAINBOARD_VENDOR="AMD"
### ###
### Build the objects we have code for in this directory. ### LinuxBIOS layout values
### ###
##object mainboard.o
driver mainboard.o ## ROM_SIZE is the size of boot ROM that this board will use.
object static_devices.o option ROM_SIZE = 524288
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
# option ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
option STACK_SIZE=0x2000
##
## Use a small 16K heap
##
option HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
##
## Compute the location and size of where this firmware image
## (linuxBIOS plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
option ROM_SECTION_SIZE = FALLBACK_SIZE
option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
else
option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
option ROM_SECTION_OFFSET = 0
end
##
## Compute the start location and size size of
## The linuxBIOS bootloader.
##
option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
option CONFIG_ROM_STREAM = 1
##
## Compute where this copy of linuxBIOS will start in the boot rom
##
option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
##
## Compute a range of ROM that can cached to speed up linuxBIOS,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
##
option XIP_ROM_SIZE=65536
option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
##
## Set all of the defaults for an x86 architecture
##
arch i386 end arch i386 end
#cpu k8 end #cpu k8 end
#
### ##
### Build our 16 bit and 32 bit linuxBIOS entry code ## Build the objects we have code for in this directory.
### ##
#object mainboard.o
driver mainboard.o
#object static_devices.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
end
makerule ./failover.inc
depends "./failover.E ./romcc"
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./auto.E ./romcc"
action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/i386/entry16.inc mainboardinit cpu/i386/entry16.inc
mainboardinit cpu/i386/entry32.inc mainboardinit cpu/i386/entry32.inc
ldscript /cpu/i386/entry16.lds ldscript /cpu/i386/entry16.lds
ldscript /cpu/i386/entry32.lds ldscript /cpu/i386/entry32.lds
#
### ##
### Build our reset vector (This is where linuxBIOS is entered) ## Build our reset vector (This is where linuxBIOS is entered)
### ##
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
mainboardinit cpu/i386/reset16.inc mainboardinit cpu/i386/reset16.inc
ldscript /cpu/i386/reset16.lds ldscript /cpu/i386/reset16.lds
@ -38,81 +182,130 @@ else
mainboardinit cpu/i386/reset32.inc mainboardinit cpu/i386/reset32.inc
ldscript /cpu/i386/reset32.lds ldscript /cpu/i386/reset32.lds
end end
#
#### Should this be in the northbridge code? ### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/cpu_reset.inc
###
### Setup the serial port ##
### ## Include an id string (For safe flashing)
#mainboardinit superiowinbond/w83627hf/setup_serial.inc ##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc
#
###
### Include an id string (For safe flashing)
###
mainboardinit arch/i386/lib/id.inc mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds ldscript /arch/i386/lib/id.lds
#
#### ##
#### This is the early phase of linuxBIOS startup ## Setup our mtrrs
#### Things are delicate and we test to see if we should ##
#### failover to another image. mainboardinit cpu/k8/earlymtrr.inc
####
#option MAX_REBOOT_CNT=2 ###
if USE_FALLBACK_IMAGE ### This is the early phase of linuxBIOS startup
ldscript /arch/i386/lib/failover.lds ### Things are delicate and we test to see if we should
end ### failover to another image.
# ###
### if USE_FALLBACK_IMAGE
### Setup our mtrrs ldscript /arch/i386/lib/failover.lds
### mainboardinit ./failover.inc
mainboardinit cpu/k8/earlymtrr.inc end
#
# ###
#### ### O.k. We aren't just an intermediary anymore!
#### O.k. We aren't just an intermediary anymore! ###
####
# ##
### ## Setup RAM
### When debugging disable the watchdog timer ##
### mainboardinit cpu/k8/enable_mmx_sse.inc
##option MAXIMUM_CONSOLE_LOGLEVEL=7 mainboardinit ./auto.inc
#default MAXIMUM_CONSOLE_LOGLEVEL=7 mainboardinit cpu/k8/disable_mmx_sse.inc
#
if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end ##
# ## Include the secondary Configuration files
### ##
### Romcc output dir /pc80
### config chip.h
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc" northbridge amd/amdk8 "mc0"
#mainboardinit .failover.inc pci 0:18.0
makerule ./auto.E pci 0:18.0
depends "$(MAINBOARD)/auto.c" pci 0:18.0
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E" pci 0:18.1
end pci 0:18.2
makerule ./auto.inc pci 0:18.3
depends "./romcc ./auto.E" southbridge amd/amd8131 "amd8131"
action "./romcc -O ./auto.E > auto.inc" pci 0:0.0
end pci 0:0.1
mainboardinit ./auto.inc pci 0:1.0
# pci 0:1.1
### end
### Include the secondary Configuration files southbridge amd/amd8111 "amd8111"
### pci 0:0.0
northbridge amd/amdk8 pci 0:1.0
end pci 0:1.1
southbridge amd/amd8111 pci 0:1.2
end pci 0:1.3
#mainboardinit archi386/smp/secondary.inc pci 0:1.5
superio NSC/pc87360 pci 0:1.6
register ".com1={1}, .com2={0}, .floppy=1, .lpt=1, .keyboard=1" superio NSC/pc87360
end pnp 1:2e.0
dir /pc80 pnp 1:2e.1
##dir /src/superio/winbond/w83627hf pnp 1:2e.2
cpu p5 end pnp 1:2e.3
cpu p6 end pnp 1:2e.4
cpu k7 end pnp 1:2e.5
cpu k8 end pnp 1:2e.6
pnp 1:2e.7
pnp 1:2e.8
pnp 1:2e.9
pnp 1:2e.a
register "com1" = "{1, 0, 0x3f8, 4}"
register "lpt" = "{1}"
end
end
end
northbridge amd/amdk8 "mc1"
pci 0:19.0
pci 0:19.0
pci 0:19.0
pci 0:19.1
pci 0:19.2
pci 0:19.3
end
northbridge amd/amdk8 "mc2"
pci 0:1a.0
pci 0:1a.0
pci 0:1a.0
pci 0:1a.1
pci 0:1a.2
pci 0:1a.3
end
northbridge amd/amdk8 "mc3"
pci 0:1b.0
pci 0:1b.0
pci 0:1b.0
pci 0:1b.1
pci 0:1b.2
pci 0:1b.3
end
cpu k8 "cpu0"
register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
end
cpu k8 "cpu1"
end
cpu k8 "cpu2"
end
cpu k8 "cpu3"
end
##
## Include the old serial code for those few places that still need it.
##
mainboardinit pc80/serial.inc
mainboardinit arch/i386/lib/console.inc

4
src/mainboard/amd/quartet/auto.c
View File

@ -25,6 +25,8 @@ static void memreset_setup(void)
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
/* Ensure the BIOS has control of the memory lines */ /* Ensure the BIOS has control of the memory lines */
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30);
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31);
} }
static void memreset(int controllers, const struct mem_controller *ctrl) static void memreset(int controllers, const struct mem_controller *ctrl)
@ -211,7 +213,7 @@ static void main(void)
enable_lapic(); enable_lapic();
init_timer(); init_timer();
if (!boot_cpu()) { if (!boot_cpu()) {
notify_bsp_ap_is_stopped(); // notify_bsp_ap_is_stopped();
stop_this_cpu(); stop_this_cpu();
} }
pc87360_enable_serial(); pc87360_enable_serial();

5
src/mainboard/amd/quartet/chip.h Normal file
View File

@ -0,0 +1,5 @@
struct chip_control mainboard_amd_quartet_control;
struct mainboard_amd_quartet_config {
int nothing;
};

40
src/mainboard/amd/quartet/irq_tables.c
View File

@ -7,25 +7,37 @@
#include <arch/pirq_routing.h> #include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = { const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */ PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */ PIRQ_VERSION, /* u16 version */
32+16*7, /* there can be total 7 devices on the bus */ 32+16*18, /* there can be total 18 devices on the bus */
0, /* Where the interrupt router lies (bus) */ 0, /* Where the interrupt router lies (bus) */
(5<<3)|3, /* Where the interrupt router lies (dev) */ 0x23, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */ 0, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */ 0x1022, /* Vendor */
0x746b, /* Device */ 0x746b, /* Device */
0, /* Crap (miniport) */ 0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , mod 256 checksum must give zero */ 0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {
{0x02, (5<<3)|0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x02, 0x00}, {0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x02, (6<<3)|0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x03, 0x00}, {0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x02, (7<<3)|0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x04, 0x00}, {0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
{0x02, (1<<3)|1, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}}, 0x00, 0x00}, {0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x00, (5<<3)|1, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00}, {0x1,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
{0x00, (2<<3)|0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00}, {0x1,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
{0xff, 0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff}, {0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
} }
}; };

33
src/mainboard/amd/quartet/mainboard.c
View File

@ -1,11 +1,42 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <arch/io.h>
#include <device/chip.h>
#include "../../../northbridge/amd/amdk8/northbridge.h"
#include "chip.h"
unsigned long initial_apicid[CONFIG_MAX_CPUS] = unsigned long initial_apicid[CONFIG_MAX_CPUS] =
{ {
0, 1, 2, 3 0, 1, 2, 3,
}; };
static struct device_operations mainboard_operations = {
.read_resources = root_dev_read_resources,
.set_resources = root_dev_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = amdk8_scan_root_bus,
.enable = 0,
};
static void enumerate(struct chip *chip)
{
struct chip *child;
dev_root.ops = &mainboard_operations;
chip->dev = &dev_root;
chip->bus = 0;
for(child = chip->children; child; child = child->next) {
child->bus = &dev_root.link[0];
}
}
struct chip_control mainboard_amd_quartet_control = {
.enumerate = enumerate,
.name = "AMD Quartet mainboard ",
};

58
src/mainboard/amd/quartet/mptable.c
View File

@ -7,8 +7,8 @@
void *smp_write_config_table(void *v, unsigned long * processor_map) void *smp_write_config_table(void *v, unsigned long * processor_map)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "AMD "; static const char oem[8] = "LNXI ";
static const char productid[12] = "QUARTET "; static const char productid[12] = "HDAMA ";
struct mp_config_table *mc; struct mp_config_table *mc;
unsigned char bus_num; unsigned char bus_num;
unsigned char bus_isa; unsigned char bus_isa;
@ -36,40 +36,40 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_processors(mc, processor_map); smp_write_processors(mc, processor_map);
{ {
struct pci_dev *dev; device_t dev;
uint32_t base;
/* 8111 */ /* 8111 */
dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) { if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++; bus_isa++;
} }
else { else {
printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 3; bus_8111_1 = 3;
bus_isa = 4; bus_isa = 4;
} }
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(0, PCI_DEVFN(0x01,0)); dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) { if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 1; bus_8131_1 = 1;
} }
/* 8131-2 */ /* 8131-2 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) { if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n"); printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 2; bus_8131_2 = 2;
} }
@ -85,17 +85,17 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
smp_write_ioapic(mc, 2, 0x11, 0xfec00000); smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
{ {
struct pci_dev *dev; device_t dev;
uint32_t base; uint32_t base;
/* 8131 apic 3 */ /* 8131 apic 3 */
dev = dev_find_slot(0, PCI_DEVFN(0x01,1)); dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) { if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK; base &= PCI_BASE_ADDRESS_MEM_MASK;
smp_write_ioapic(mc, 0x03, 0x11, base); smp_write_ioapic(mc, 0x03, 0x11, base);
} }
/* 8131 apic 4 */ /* 8131 apic 4 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,1)); dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) { if (dev) {
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
base &= PCI_BASE_ADDRESS_MEM_MASK; base &= PCI_BASE_ADDRESS_MEM_MASK;
@ -150,43 +150,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
/* PCI Slot 1 */ /* PCI Slot 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (1<<2)|0, 0x04, 0x1); bus_8131_2, (1<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (1<<2)|1, 0x04, 0x2); bus_8131_2, (1<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (1<<2)|2, 0x04, 0x3); bus_8131_2, (1<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (1<<2)|3, 0x04, 0x0); bus_8131_2, (1<<2)|3, 0x02, 0x10);
/* PCI Slot 2 */ /* PCI Slot 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (2<<2)|0, 0x04, 0x2); bus_8131_2, (2<<2)|0, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (2<<2)|1, 0x04, 0x3); bus_8131_2, (2<<2)|1, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (2<<2)|2, 0x04, 0x0); bus_8131_2, (2<<2)|2, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_2, (2<<2)|3, 0x04, 0x1); bus_8131_2, (2<<2)|3, 0x02, 0x11);
/* PCI Slot 3 */ /* PCI Slot 3 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (1<<2)|0, 0x03, 0x1); bus_8131_1, (1<<2)|0, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (1<<2)|1, 0x03, 0x2); bus_8131_1, (1<<2)|1, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (1<<2)|2, 0x03, 0x3); bus_8131_1, (1<<2)|2, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (1<<2)|3, 0x03, 0x0); bus_8131_1, (1<<2)|3, 0x02, 0x10);
/* PCI Slot 4 */ /* PCI Slot 4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (2<<2)|0, 0x03, 0x2); bus_8131_1, (2<<2)|0, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (2<<2)|1, 0x03, 0x3); bus_8131_1, (2<<2)|1, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (2<<2)|2, 0x03, 0x0); bus_8131_1, (2<<2)|2, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_8131_1, (2<<2)|3, 0x03, 0x1); bus_8131_1, (2<<2)|3, 0x02, 0x11);
/* PCI Slot 5 */ /* PCI Slot 5 */
#warning "FIXME get the irqs right, it's just hacked to work for now" #warning "FIXME get the irqs right, it's just hacked to work for now"

10
src/mainboard/amd/quartet/resourcemap.c
View File

@ -34,10 +34,10 @@ static void setup_quartet_resource_map(void)
* This field defines the upper address bits of a 40 bit address * This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region. * that define the end of the DRAM region.
*/ */
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00f00000, PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x000f0000,
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x01f00001, PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x001f0001,
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x02f00002, PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x002f0002,
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x03f00003, PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x003f0003,
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
@ -256,7 +256,7 @@ static void setup_quartet_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000203, PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000203,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0xff080113, PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0xff080113,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xffff0040, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xffff0040,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0xffff0330, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0xffff0270,
}; };
int max; int max;
max = sizeof(register_values)/sizeof(register_values[0]); max = sizeof(register_values)/sizeof(register_values[0]);