remove old config files, adopt to new config method. fix resource map (?)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
dad60489d5
commit
5282cd0875
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@ -1,36 +1,180 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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#
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#
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uses MAINBOARD
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uses ARCH
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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###
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### Set all of the defaults for an x86 architecture
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### Build options
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###
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#
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#
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option CONFIG_SMP=1
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option CONFIG_MAX_CPUS=4
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##
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## Build code to setup a generic IOAPIC
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##
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option CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER="QUARTET"
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option MAINBOARD_VENDOR="AMD"
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###
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### Build the objects we have code for in this directory.
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### LinuxBIOS layout values
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###
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##object mainboard.o
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driver mainboard.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE = 524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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option HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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option ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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option XIP_ROM_SIZE=65536
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option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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##
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## Build the objects we have code for in this directory.
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##
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#object mainboard.o
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driver mainboard.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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@ -38,81 +182,130 @@ else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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#
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -O ./auto.E > auto.inc"
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end
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mainboardinit ./auto.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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end
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southbridge amd/amd8111
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register ".com1={1}, .com2={0}, .floppy=1, .lpt=1, .keyboard=1"
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end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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cpu p5 end
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cpu p6 end
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cpu k7 end
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cpu k8 end
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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###
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### O.k. We aren't just an intermediary anymore!
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###
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##
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## Setup RAM
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##
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131"
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111"
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pci 0:0.0
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pci 0:1.0
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pci 0:1.1
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pci 0:1.2
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pci 0:1.3
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pci 0:1.5
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pci 0:1.6
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superio NSC/pc87360
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pnp 1:2e.0
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pnp 1:2e.1
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pnp 1:2e.2
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pnp 1:2e.3
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pnp 1:2e.4
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pnp 1:2e.5
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pnp 1:2e.6
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pnp 1:2e.7
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pnp 1:2e.8
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pnp 1:2e.9
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pnp 1:2e.a
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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northbridge amd/amdk8 "mc2"
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.1
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pci 0:1a.2
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pci 0:1a.3
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end
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northbridge amd/amdk8 "mc3"
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.1
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pci 0:1b.2
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pci 0:1b.3
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end
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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end
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cpu k8 "cpu2"
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end
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cpu k8 "cpu3"
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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@ -25,6 +25,8 @@ static void memreset_setup(void)
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 30);
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 31);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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@ -211,7 +213,7 @@ static void main(void)
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enable_lapic();
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init_timer();
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if (!boot_cpu()) {
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notify_bsp_ap_is_stopped();
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// notify_bsp_ap_is_stopped();
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stop_this_cpu();
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}
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pc87360_enable_serial();
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@ -0,0 +1,5 @@
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struct chip_control mainboard_amd_quartet_control;
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struct mainboard_amd_quartet_config {
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int nothing;
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};
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@ -7,25 +7,37 @@
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*7, /* there can be total 7 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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(5<<3)|3, /* Where the interrupt router lies (dev) */
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0xc20, /* IRQs devoted exclusively to PCI usage */
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32+16*18, /* there can be total 18 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0x23, /* Where the interrupt router lies (dev) */
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0, /* IRQs devoted exclusively to PCI usage */
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0x1022, /* Vendor */
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0x746b, /* Device */
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0, /* Crap (miniport) */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0xdf, /* u8 checksum , mod 256 checksum must give zero */
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{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x02, (5<<3)|0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x02, 0x00},
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{0x02, (6<<3)|0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x03, 0x00},
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{0x02, (7<<3)|0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x04, 0x00},
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{0x02, (1<<3)|1, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}}, 0x00, 0x00},
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{0x00, (5<<3)|1, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
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{0x00, (2<<3)|0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
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{0xff, 0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff},
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0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
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{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
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{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x1,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
|
||||
{0x1,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x0, 0},
|
||||
{0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
|
||||
{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
|
||||
{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
|
||||
{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
|
||||
{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
|
||||
{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
|
||||
{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
|
||||
{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,11 +1,42 @@
|
|||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/chip.h>
|
||||
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||
#include "chip.h"
|
||||
|
||||
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0, 1, 2, 3
|
||||
0, 1, 2, 3,
|
||||
};
|
||||
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_amd_quartet_control = {
|
||||
.enumerate = enumerate,
|
||||
.name = "AMD Quartet mainboard ",
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@
|
|||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "AMD ";
|
||||
static const char productid[12] = "QUARTET ";
|
||||
static const char oem[8] = "LNXI ";
|
||||
static const char productid[12] = "HDAMA ";
|
||||
struct mp_config_table *mc;
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
|
|
@ -36,40 +36,40 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_processors(mc, processor_map);
|
||||
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
device_t dev;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:03.0, using defaults\n");
|
||||
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 3;
|
||||
bus_isa = 4;
|
||||
}
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x01,0));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:01.0, using defaults\n");
|
||||
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||
|
||||
bus_8131_1 = 1;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 0:02.0, using defaults\n");
|
||||
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_8131_2 = 2;
|
||||
}
|
||||
|
|
@ -85,17 +85,17 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
device_t dev;
|
||||
uint32_t base;
|
||||
/* 8131 apic 3 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x01,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 0x03, 0x11, base);
|
||||
}
|
||||
/* 8131 apic 4 */
|
||||
dev = dev_find_slot(0, PCI_DEVFN(0x02,1));
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
|
|
@ -150,43 +150,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
|
||||
/* PCI Slot 1 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|0, 0x04, 0x1);
|
||||
bus_8131_2, (1<<2)|0, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|1, 0x04, 0x2);
|
||||
bus_8131_2, (1<<2)|1, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|2, 0x04, 0x3);
|
||||
bus_8131_2, (1<<2)|2, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (1<<2)|3, 0x04, 0x0);
|
||||
bus_8131_2, (1<<2)|3, 0x02, 0x10);
|
||||
|
||||
/* PCI Slot 2 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|0, 0x04, 0x2);
|
||||
bus_8131_2, (2<<2)|0, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|1, 0x04, 0x3);
|
||||
bus_8131_2, (2<<2)|1, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|2, 0x04, 0x0);
|
||||
bus_8131_2, (2<<2)|2, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_2, (2<<2)|3, 0x04, 0x1);
|
||||
bus_8131_2, (2<<2)|3, 0x02, 0x11);
|
||||
|
||||
/* PCI Slot 3 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|0, 0x03, 0x1);
|
||||
bus_8131_1, (1<<2)|0, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|1, 0x03, 0x2);
|
||||
bus_8131_1, (1<<2)|1, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|2, 0x03, 0x3);
|
||||
bus_8131_1, (1<<2)|2, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (1<<2)|3, 0x03, 0x0);
|
||||
bus_8131_1, (1<<2)|3, 0x02, 0x10);
|
||||
|
||||
/* PCI Slot 4 */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|0, 0x03, 0x2);
|
||||
bus_8131_1, (2<<2)|0, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|1, 0x03, 0x3);
|
||||
bus_8131_1, (2<<2)|1, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|2, 0x03, 0x0);
|
||||
bus_8131_1, (2<<2)|2, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8131_1, (2<<2)|3, 0x03, 0x1);
|
||||
bus_8131_1, (2<<2)|3, 0x02, 0x11);
|
||||
|
||||
/* PCI Slot 5 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
|
|
|
|||
|
|
@ -34,10 +34,10 @@ static void setup_quartet_resource_map(void)
|
|||
* This field defines the upper address bits of a 40 bit address
|
||||
* that define the end of the DRAM region.
|
||||
*/
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00f00000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x01f00001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x02f00002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x03f00003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x000f0000,
|
||||
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x001f0001,
|
||||
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x002f0002,
|
||||
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x003f0003,
|
||||
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||
|
|
@ -256,7 +256,7 @@ static void setup_quartet_resource_map(void)
|
|||
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000203,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0xff080113,
|
||||
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xffff0040,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0xffff0330,
|
||||
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0xffff0270,
|
||||
};
|
||||
int max;
|
||||
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||
|
|
|
|||
Loading…
Reference in New Issue