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soc/intel/cannonlake: Disable CpuRatio and SaGv in recovery 

Disabling CpuRatio UPD for FSP will ensure it does not force a
hard reset to set the CPU Flex Ratio at boot.  This is important
in a recovery mode boot where the SOC will lose power and need
to set the flex ratio again.

Disabling SaGv makes recovery mode training faster and mirrors
the setting that was done on Skylake.

BUG=b:123305400
TEST=reliably enter recovery mode on sarien

Change-Id: Ie9664493a980af9acce82faff81f4c4b1355be73
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2019-01-23 14:55:47 -08:00 committed by Patrick Georgi
parent 38e40414d2
commit 52b5b587f1
1 changed files with 17 additions and 0 deletions
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17
src/soc/intel/cannonlake/romstage/fsp_params.c
View File

@ -17,9 +17,11 @@
#include <chip.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
{
@ -54,6 +56,21 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
#endif
/* Disable CPU Flex Ratio and SaGv in recovery mode */
if (vboot_recovery_mode_enabled()) {
struct chipset_power_state *ps = pmc_get_power_state();
/*
* Only disable when coming from S5 (cold reset) otherwise
* the flex ratio may be locked and FSP will return an error.
*/
if (ps && ps->prev_sleep_state == ACPI_S5) {
m_cfg->CpuRatio = 0;
m_cfg->SaGv = 0;
}
}
/* If ISH is enabled, enable ISH elements */
if (!dev)
m_cfg->PchIshEnable = 0;