broadwell boards: Switch to Lynxpoint GPIO headers

Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.

Tested with BUILD_TIMELESS=1, Google Tidus remains identical.

Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/chromeos.c

@@ -2,7 +2,8 @@
 
 #include <boot/coreboot_tables.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
+#include <soc/chromeos.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 
 /* SPI Write protect is GPIO 16 */
 #define CROS_WP_GPIO	58

src/mainboard/google/auron/smihandler.c

@@ -7,7 +7,7 @@
 #include <soc/pm.h>
 #include <elog.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/iomap.h>
 #include <soc/nvs.h>
 #include "ec.h"

src/mainboard/google/auron/spd.c

@@ -3,7 +3,7 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <mainboard/google/auron/variant.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <string.h>

src/mainboard/google/auron/variants/auron_paine/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/auron_paine/spd/spd.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <string.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/auron/variants/auron_yuna/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/auron_yuna/spd/spd.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <string.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/auron/variants/buddy/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/gandof/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/gandof/spd/spd.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <string.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/auron/variants/lulu/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/lulu/spd/spd.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <string.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/auron/variants/samus/pei_data.c

@@ -2,7 +2,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/auron/variants/samus/spd/spd.c

@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <endian.h>
 #include <string.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/auron/variants/samus/variant.c

@@ -2,7 +2,7 @@
 
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <smbios.h>

src/mainboard/google/jecht/chromeos.c

@@ -5,8 +5,9 @@
 #include <device/device.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <soc/chromeos.h>
 #include <soc/sata.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include "onboard.h"
 
 #define GPIO_SPI_WP	58

src/mainboard/google/jecht/smihandler.c

@@ -5,7 +5,7 @@
 #include <cpu/x86/smm.h>
 #include <soc/pm.h>
 #include <ec/google/chromeec/ec.h>
-#include <soc/gpio.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/iomap.h>
 #include <soc/nvs.h>
 #include "onboard.h"

src/mainboard/google/jecht/variants/guado/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/jecht/variants/jecht/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/jecht/variants/rikku/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/google/jecht/variants/tidus/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/mainboard/intel/wtm2/chromeos.c

@@ -3,7 +3,8 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <device/device.h>
-#include <soc/gpio.h>
+#include <soc/chromeos.h>
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 /* Compile-time settings for recovery mode. */

src/mainboard/intel/wtm2/pei_data.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <soc/gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
 

src/soc/intel/broadwell/include/soc/chromeos.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _BROADWELL_CHROMEOS_H_
+#define _BROADWELL_CHROMEOS_H_
+
+#define CROS_GPIO_DEVICE_NAME		"PCH-LP"
+
+#endif

src/soc/intel/broadwell/include/soc/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _BROADWELL_GPIO_H_
-#define _BROADWELL_GPIO_H_
-
-#include <stdint.h>
-
-#define CROS_GPIO_DEVICE_NAME		"PCH-LP"
-#define CROS_GPIO_ACPI_DEVICE_NAME	"INT3437:00"
-
-#include <southbridge/intel/lynxpoint/lp_gpio.h>
-
-#endif