nb/intel/sandybridge: Drop `pci_mmio_size`

There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.

Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-04-02 22:55:00 +02:00
parent f2e8660fa2
commit 5304ce108e
8 changed files with 3 additions and 36 deletions

View File

@ -33,8 +33,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge

View File

@ -26,8 +26,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0x0 on
subsystemid 0x17aa 0x21fe inherit

View File

@ -24,8 +24,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
subsystemid 0x17aa 0x21f9 inherit

View File

@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
subsystemid 0x17aa 0x21fa inherit

View File

@ -31,8 +31,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
ioapic_irq 4 INTA 0x10
ioapic_irq 4 INTB 0x11

View File

@ -23,8 +23,6 @@ chip northbridge/intel/sandybridge
end
end
register "pci_mmio_size" = "1024"
device domain 0 on
subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge

View File

@ -43,11 +43,6 @@ struct northbridge_intel_sandybridge_config {
struct i915_gpu_controller_info gfx;
/*
* Maximum PCI MMIO size in MiB.
*/
u16 pci_mmio_size;
/* Data for RAM init */
/* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */

View File

@ -338,24 +338,6 @@ void dram_zones(ramctr_timing *ctrl, int training)
}
}
#define DEFAULT_PCI_MMIO_SIZE 2048
static unsigned int get_mmio_size(void)
{
const struct device *dev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
if (dev)
cfg = dev->chip_info;
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->pci_mmio_size == 0)
return DEFAULT_PCI_MMIO_SIZE;
else
return cfg->pci_mmio_size;
}
/*
* Returns the ECC mode the NB is running at. It takes precedence over ECC capability.
* The ME/PCU/.. has the ability to change this.
@ -382,6 +364,8 @@ bool get_host_ecc_cap(void)
return !(reg32 & (1 << 25));
}
#define DEFAULT_PCI_MMIO_SIZE 2048
void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
{
u32 reg, val, reclaim, tom, gfxstolen, gttsize;
@ -389,7 +373,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta;
uint16_t ggc;
mmiosize = get_mmio_size();
mmiosize = DEFAULT_PCI_MMIO_SIZE;
ggc = pci_read_config16(HOST_BRIDGE, GGC);
if (!(ggc & 2)) {