nb/intel/sandybridge: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it increases available DRAM in 32-bit space. However, as this is a 64-bit platform, it's highly unlikely that 32-bit limitations would cause any issues anymore. It's more likely to have the allocator give up because memory-mapped resources in 32-bit space don't fit within the specified MMIO size, which can easily occur when using a discrete graphics card. Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,8 +33,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0 on
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subsystemid 0x1ae0 0xc000 inherit
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device pci 00.0 on end # host bridge
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@ -26,8 +26,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0x0 on
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subsystemid 0x17aa 0x21fe inherit
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@ -24,8 +24,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0 on
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subsystemid 0x17aa 0x21f9 inherit
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@ -27,8 +27,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0 on
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subsystemid 0x17aa 0x21fa inherit
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@ -31,8 +31,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0 on
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ioapic_irq 4 INTA 0x10
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ioapic_irq 4 INTB 0x11
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@ -23,8 +23,6 @@ chip northbridge/intel/sandybridge
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end
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end
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register "pci_mmio_size" = "1024"
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device domain 0 on
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subsystemid 0x1ae0 0xc000 inherit
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device pci 00.0 on end # host bridge
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@ -43,11 +43,6 @@ struct northbridge_intel_sandybridge_config {
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struct i915_gpu_controller_info gfx;
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/*
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* Maximum PCI MMIO size in MiB.
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*/
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u16 pci_mmio_size;
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/* Data for RAM init */
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/* DIMM SPD address. Use 8bit notation where BIT0 is always zero. */
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@ -338,24 +338,6 @@ void dram_zones(ramctr_timing *ctrl, int training)
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}
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}
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#define DEFAULT_PCI_MMIO_SIZE 2048
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static unsigned int get_mmio_size(void)
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{
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const struct device *dev;
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const struct northbridge_intel_sandybridge_config *cfg = NULL;
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dev = pcidev_path_on_root(PCI_DEVFN(0, 0));
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if (dev)
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cfg = dev->chip_info;
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/* If this is zero, it just means devicetree.cb didn't set it */
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if (!cfg || cfg->pci_mmio_size == 0)
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return DEFAULT_PCI_MMIO_SIZE;
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else
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return cfg->pci_mmio_size;
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}
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/*
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* Returns the ECC mode the NB is running at. It takes precedence over ECC capability.
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* The ME/PCU/.. has the ability to change this.
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@ -382,6 +364,8 @@ bool get_host_ecc_cap(void)
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return !(reg32 & (1 << 25));
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}
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#define DEFAULT_PCI_MMIO_SIZE 2048
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void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
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{
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u32 reg, val, reclaim, tom, gfxstolen, gttsize;
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@ -389,7 +373,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
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size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta;
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uint16_t ggc;
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mmiosize = get_mmio_size();
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mmiosize = DEFAULT_PCI_MMIO_SIZE;
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ggc = pci_read_config16(HOST_BRIDGE, GGC);
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if (!(ggc & 2)) {
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