sb/amd/rs780: Get rid of device_t
Change-Id: Ica3b6f2d0b270930df77d528e70bd15972da8757 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki
parent
a211c1bf94
commit
532001ae73
|
|
@ -27,20 +27,20 @@
|
|||
#include <cpu/cpu.h>
|
||||
#include "rs780.h"
|
||||
|
||||
static u32 nb_read_index(device_t dev, u32 index_reg, u32 index)
|
||||
static u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
|
||||
{
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
return pci_read_config32(dev, index_reg + 0x4);
|
||||
}
|
||||
|
||||
static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data)
|
||||
static void nb_write_index(struct device *dev, u32 index_reg, u32 index, u32 data)
|
||||
{
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
pci_write_config32(dev, index_reg + 0x4, data);
|
||||
}
|
||||
|
||||
/* extension registers */
|
||||
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
|
||||
u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)
|
||||
{
|
||||
/* get BAR3 base address for nbcfg0x1c */
|
||||
u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
|
||||
|
|
@ -51,7 +51,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
|
|||
return *((u32 *) addr);
|
||||
}
|
||||
|
||||
void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
||||
|
|
@ -70,57 +70,57 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask
|
|||
}
|
||||
}
|
||||
|
||||
u32 nbmisc_read_index(device_t nb_dev, u32 index)
|
||||
u32 nbmisc_read_index(struct device *nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbmisc_write_index(device_t nb_dev, u32 index, u32 data)
|
||||
void nbmisc_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
|
||||
}
|
||||
|
||||
u32 nbpcie_p_read_index(device_t dev, u32 index)
|
||||
u32 nbpcie_p_read_index(struct device *dev, u32 index)
|
||||
{
|
||||
return nb_read_index((dev), NBPCIE_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbpcie_p_write_index(device_t dev, u32 index, u32 data)
|
||||
void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((dev), NBPCIE_INDEX, (index), (data));
|
||||
}
|
||||
|
||||
u32 nbpcie_ind_read_index(device_t nb_dev, u32 index)
|
||||
u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
|
||||
void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
|
||||
}
|
||||
|
||||
u32 htiu_read_index(device_t nb_dev, u32 index)
|
||||
u32 htiu_read_index(struct device *nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
|
||||
}
|
||||
|
||||
void htiu_write_index(device_t nb_dev, u32 index, u32 data)
|
||||
void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
|
||||
}
|
||||
|
||||
u32 nbmc_read_index(device_t nb_dev, u32 index)
|
||||
u32 nbmc_read_index(struct device *nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMC_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbmc_write_index(device_t nb_dev, u32 index, u32 data)
|
||||
void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
|
||||
}
|
||||
|
||||
void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = pci_read_config32(nb_dev, reg_pos);
|
||||
|
|
@ -131,7 +131,7 @@ void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
|
||||
void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, u8 mask, u8 val)
|
||||
{
|
||||
u8 reg_old, reg;
|
||||
reg = reg_old = pci_read_config8(nb_dev, reg_pos);
|
||||
|
|
@ -142,7 +142,7 @@ void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val)
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
|
||||
|
|
@ -153,7 +153,7 @@ void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = htiu_read_index(nb_dev, reg_pos);
|
||||
|
|
@ -164,7 +164,7 @@ void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
|
||||
|
|
@ -175,7 +175,7 @@ void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val)
|
|||
}
|
||||
}
|
||||
|
||||
void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
|
||||
void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
|
||||
|
|
@ -195,8 +195,8 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val)
|
|||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
|
||||
{
|
||||
/* K8 Function1 is address map */
|
||||
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
|
||||
if (in_out) {
|
||||
u32 dword, sblk;
|
||||
|
|
@ -222,7 +222,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
|
|||
}
|
||||
}
|
||||
|
||||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
|
||||
void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
switch (port) {
|
||||
case 2: /* GFX, bit4-5 */
|
||||
|
|
@ -250,7 +250,7 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
|
|||
* 0: no device is present.
|
||||
* 1: device is present and is trained.
|
||||
*/
|
||||
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
|
||||
u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u16 count = 5000;
|
||||
u32 lc_state, reg, current_link_width, lane_mask;
|
||||
|
|
@ -346,7 +346,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
|
|||
* Compliant with CIM_33's ATINB_SetToms.
|
||||
* Set Top Of Memory below and above 4G.
|
||||
*/
|
||||
void rs780_set_tom(device_t nb_dev)
|
||||
void rs780_set_tom(struct device *nb_dev)
|
||||
{
|
||||
/* set TOM */
|
||||
#if IS_ENABLED(CONFIG_GFXUMA)
|
||||
|
|
|
|||
|
|
@ -38,37 +38,37 @@ static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
|
|||
pci_write_config32(dev, index_reg + 0x4, data);
|
||||
}
|
||||
|
||||
u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
static u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
static void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
|
||||
}
|
||||
|
||||
u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
static u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
|
||||
}
|
||||
|
||||
void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
static void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
|
||||
}
|
||||
|
||||
u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
static u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMC_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
static void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
|
||||
}
|
||||
|
||||
void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
static void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
|
@ -80,7 +80,7 @@ void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
static void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
|
@ -92,7 +92,7 @@ void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
static void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
|
@ -121,7 +121,7 @@ static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev, u32 reg_pos,
|
|||
#endif
|
||||
|
||||
|
||||
void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
|
||||
static void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
|
||||
u8 val)
|
||||
{
|
||||
u8 reg_old, reg;
|
||||
|
|
@ -133,7 +133,7 @@ void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask,
|
|||
}
|
||||
}
|
||||
|
||||
void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
static void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask,
|
||||
u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ void set_pcie_dereset(void);
|
|||
ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;
|
||||
|
||||
#ifdef UNUSED_CODE
|
||||
static u32 clkind_read(device_t dev, u32 index)
|
||||
static u32 clkind_read(struct device *dev, u32 index)
|
||||
{
|
||||
u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
|
||||
|
||||
|
|
@ -59,7 +59,7 @@ static u32 clkind_read(device_t dev, u32 index)
|
|||
}
|
||||
#endif
|
||||
|
||||
static void clkind_write(device_t dev, u32 index, u32 data)
|
||||
static void clkind_write(struct device *dev, u32 index, u32 data)
|
||||
{
|
||||
u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
|
||||
/* printk(BIOS_DEBUG, "gfx bar 2 %02x\n", gfx_bar2); */
|
||||
|
|
@ -72,7 +72,7 @@ static void clkind_write(device_t dev, u32 index, u32 data)
|
|||
* pci_dev_read_resources thinks it is a IO type.
|
||||
* We have to force it to mem type.
|
||||
*/
|
||||
static void rs780_gfx_read_resources(device_t dev)
|
||||
static void rs780_gfx_read_resources(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "rs780_gfx_read_resources.\n");
|
||||
|
||||
|
|
@ -177,8 +177,8 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
|
|||
CIM_STATUS Status = CIM_UNSUPPORTED;
|
||||
u8 Bus, Dev, Reg, BusStart, BusEnd;
|
||||
u32 Value;
|
||||
device_t dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
device_t tempdev;
|
||||
struct device *dev0x14 = dev_find_slot(0, PCI_DEVFN(0x14, 4));
|
||||
struct device *tempdev;
|
||||
Value = pci_read_config32(dev0x14, 0x18);
|
||||
BusStart = (Value >> 8) & 0xFF;
|
||||
BusEnd = (Value >> 16) & 0xFF;
|
||||
|
|
@ -235,7 +235,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
|
|||
static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
|
||||
{
|
||||
int i, j, n = 7;
|
||||
device_t k8_f1;
|
||||
struct device *k8_f1;
|
||||
|
||||
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
|
||||
|
|
@ -294,7 +294,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
|
|||
* Lanes 12-13 Bit 14 Bit 6
|
||||
* Lanes 14-15 Bit 15 Bit 7
|
||||
*/
|
||||
static void poweron_ddi_lanes(device_t nb_dev)
|
||||
static void poweron_ddi_lanes(struct device *nb_dev)
|
||||
{
|
||||
u8 i;
|
||||
u32 gfx_cfg = 0;
|
||||
|
|
@ -321,9 +321,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
|
|||
u16 command;
|
||||
u32 value;
|
||||
u16 deviceid, vendorid;
|
||||
device_t nb_dev = dev_find_slot(0, 0);
|
||||
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
|
||||
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
struct device *nb_dev = dev_find_slot(0, 0);
|
||||
struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
|
||||
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
static const u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32};
|
||||
static const u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0};
|
||||
static const u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200};
|
||||
|
|
@ -732,10 +732,10 @@ static void internal_gfx_pci_dev_init(struct device *dev)
|
|||
* Set registers in RS780 and CPU to disable the internal GFX.
|
||||
* Please refer to `rs780_internal_gfx_enable()`.
|
||||
*/
|
||||
static void rs780_internal_gfx_disable(device_t dev)
|
||||
static void rs780_internal_gfx_disable(struct device *dev)
|
||||
{
|
||||
u32 l_dword;
|
||||
device_t nb_dev = dev_find_slot(0, 0);
|
||||
struct device *nb_dev = dev_find_slot(0, 0);
|
||||
|
||||
/* Disable internal GFX and enable external GFX. */
|
||||
l_dword = pci_read_config32(nb_dev, 0x8c);
|
||||
|
|
@ -751,11 +751,11 @@ static void rs780_internal_gfx_disable(device_t dev)
|
|||
* Please refer to CIM source code and BKDG.
|
||||
*/
|
||||
|
||||
static void rs780_internal_gfx_enable(device_t dev)
|
||||
static void rs780_internal_gfx_enable(struct device *dev)
|
||||
{
|
||||
u32 l_dword;
|
||||
int i;
|
||||
device_t nb_dev = dev_find_slot(0, 0);
|
||||
struct device *nb_dev = dev_find_slot(0, 0);
|
||||
msr_t sysmem;
|
||||
|
||||
#if !IS_ENABLED(CONFIG_GFXUMA)
|
||||
|
|
@ -789,7 +789,7 @@ static void rs780_internal_gfx_enable(device_t dev)
|
|||
|
||||
/* LPC DMA Deadlock workaround? */
|
||||
/* GFX_InitCommon*/
|
||||
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
struct device *k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
l_dword = pci_read_config32(k8_f0, 0x68);
|
||||
l_dword &= ~(3 << 21);
|
||||
l_dword |= (1 << 21);
|
||||
|
|
@ -804,9 +804,9 @@ static void rs780_internal_gfx_enable(device_t dev)
|
|||
#if IS_ENABLED(CONFIG_GFXUMA)
|
||||
/* GFX_InitUMA. */
|
||||
/* Copy CPU DDR Controller to NB MC. */
|
||||
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
|
||||
device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
|
||||
struct device *k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
struct device *k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
|
||||
struct device *k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
|
||||
for (i = 0; i < 12; i++) {
|
||||
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
|
||||
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
|
||||
|
|
@ -1007,7 +1007,7 @@ static const struct pci_driver pcie_driver_780 __pci_driver = {
|
|||
};
|
||||
|
||||
/* step 12 ~ step 14 from rpr */
|
||||
static void single_port_configuration(device_t nb_dev, device_t dev)
|
||||
static void single_port_configuration(struct device *nb_dev, struct device *dev)
|
||||
{
|
||||
u8 result, width;
|
||||
u32 reg32;
|
||||
|
|
@ -1064,7 +1064,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev)
|
|||
printk(BIOS_DEBUG, "rs780_gfx_init single_port_configuration step14.\n");
|
||||
}
|
||||
|
||||
static void dual_port_configuration(device_t nb_dev, device_t dev)
|
||||
static void dual_port_configuration(struct device *nb_dev, struct device *dev)
|
||||
{
|
||||
u8 result, width;
|
||||
u32 reg32, dev_ind = dev->path.pci.devfn >> 3;
|
||||
|
|
@ -1120,10 +1120,10 @@ static void dual_port_configuration(device_t nb_dev, device_t dev)
|
|||
* 101 = x12 (not supported)
|
||||
* 110 = x16
|
||||
*/
|
||||
static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
|
||||
static void dynamic_link_width_control(struct device *nb_dev, struct device *dev, u8 width)
|
||||
{
|
||||
u32 reg32;
|
||||
device_t sb_dev;
|
||||
struct device *sb_dev;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
(struct southbridge_amd_rs780_config *)nb_dev->chip_info;
|
||||
|
||||
|
|
@ -1166,7 +1166,7 @@ static void dynamic_link_width_control(device_t nb_dev, device_t dev, u8 width)
|
|||
/*
|
||||
* GFX Core initialization, dev2, dev3
|
||||
*/
|
||||
void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
|
||||
void rs780_gfx_init(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u32 reg32;
|
||||
struct southbridge_amd_rs780_config *cfg =
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@
|
|||
#include "rs780.h"
|
||||
|
||||
/* for UMA internal graphics */
|
||||
void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev)
|
||||
void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
device_t cpu_f0;
|
||||
struct device *cpu_f0;
|
||||
u8 reg;
|
||||
|
||||
cpu_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
/*****************************************
|
||||
* rs780_config_misc_clk()
|
||||
*****************************************/
|
||||
void static rs780_config_misc_clk(device_t nb_dev)
|
||||
void static rs780_config_misc_clk(struct device *nb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
u16 word;
|
||||
|
|
@ -104,12 +104,12 @@ void static rs780_config_misc_clk(device_t nb_dev)
|
|||
set_htiu_enable_bits(nb_dev, 0x05, 7 << 8, 7 << 8);
|
||||
}
|
||||
|
||||
static u32 get_vid_did(device_t dev)
|
||||
static u32 get_vid_did(struct device *dev)
|
||||
{
|
||||
return pci_read_config32(dev, 0);
|
||||
}
|
||||
|
||||
static void rs780_nb_pci_table(device_t nb_dev)
|
||||
static void rs780_nb_pci_table(struct device *nb_dev)
|
||||
{ /* NBPOR_InitPOR function. */
|
||||
u8 temp8;
|
||||
u16 temp16;
|
||||
|
|
@ -183,7 +183,7 @@ static void rs780_nb_pci_table(device_t nb_dev)
|
|||
#endif
|
||||
}
|
||||
|
||||
static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
|
||||
static void rs780_nb_gfx_dev_table(struct device *nb_dev, struct device *dev)
|
||||
{
|
||||
/* NB_InitGFXStraps */
|
||||
u32 MMIOBase, apc04, apc18, apc24, romstrap2;
|
||||
|
|
@ -265,9 +265,9 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
|
|||
* case 0 will be called twice, one is by CPU in hypertransport.c line458,
|
||||
* the other is by rs780.
|
||||
***********************************************/
|
||||
void rs780_enable(device_t dev)
|
||||
void rs780_enable(struct device *dev)
|
||||
{
|
||||
device_t nb_dev = 0, sb_dev = 0;
|
||||
struct device *nb_dev = NULL, *sb_dev = NULL;
|
||||
int dev_ind;
|
||||
|
||||
printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#ifndef __RS780_H__
|
||||
#define __RS780_H__
|
||||
|
||||
#include <rules.h>
|
||||
#include <stdint.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "chip.h"
|
||||
|
|
@ -170,47 +171,56 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
|
|||
* ------------------------------------------------- */
|
||||
extern PCIE_CFG AtiPcieCfg;
|
||||
|
||||
#if ENV_RAMSTAGE
|
||||
/* ----------------- export functions ----------------- */
|
||||
u32 nbmisc_read_index(device_t nb_dev, u32 index);
|
||||
void nbmisc_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbpcie_p_read_index(device_t dev, u32 index);
|
||||
void nbpcie_p_write_index(device_t dev, u32 index, u32 data);
|
||||
u32 nbpcie_ind_read_index(device_t nb_dev, u32 index);
|
||||
void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 htiu_read_index(device_t nb_dev, u32 index);
|
||||
void htiu_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbmc_read_index(device_t nb_dev, u32 index);
|
||||
void nbmc_write_index(device_t nb_dev, u32 index, u32 data);
|
||||
u32 nbmisc_read_index(struct device * nb_dev, u32 index);
|
||||
void nbmisc_write_index(struct device * nb_dev, u32 index, u32 data);
|
||||
u32 nbpcie_p_read_index(struct device * dev, u32 index);
|
||||
void nbpcie_p_write_index(struct device * dev, u32 index, u32 data);
|
||||
u32 nbpcie_ind_read_index(struct device * nb_dev, u32 index);
|
||||
void nbpcie_ind_write_index(struct device * nb_dev, u32 index, u32 data);
|
||||
u32 htiu_read_index(struct device * nb_dev, u32 index);
|
||||
void htiu_write_index(struct device * nb_dev, u32 index, u32 data);
|
||||
u32 nbmc_read_index(struct device * nb_dev, u32 index);
|
||||
void nbmc_write_index(struct device * nb_dev, u32 index, u32 data);
|
||||
|
||||
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg);
|
||||
void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val);
|
||||
u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);
|
||||
void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg, u32 mask, u32 val);
|
||||
|
||||
void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_nbcfg_enable_bits_8(device_t nb_dev, u32 reg_pos, u8 mask, u8 val);
|
||||
void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_htiu_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_nbmisc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void rs780_set_tom(device_t nb_dev);
|
||||
void set_nbcfg_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_nbcfg_enable_bits_8(struct device * nb_dev, u32 reg_pos, u8 mask, u8 val);
|
||||
void set_nbmc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void set_htiu_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
|
||||
void set_nbmisc_enable_bits(struct device * nb_dev, u32 reg_pos, u32 mask, u32 val);
|
||||
|
||||
void set_pcie_enable_bits(struct device *dev, u32 reg_pos, u32 mask, u32 val);
|
||||
void rs780_set_tom(struct device *nb_dev);
|
||||
|
||||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
|
||||
void enable_pcie_bar3(device_t nb_dev);
|
||||
void disable_pcie_bar3(device_t nb_dev);
|
||||
void enable_pcie_bar3(struct device *nb_dev);
|
||||
void disable_pcie_bar3(struct device *nb_dev);
|
||||
|
||||
void rs780_enable(struct device *dev);
|
||||
void rs780_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void rs780_gfx_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev);
|
||||
void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port);
|
||||
u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);
|
||||
|
||||
void pcie_hide_unused_ports(struct device *nb_dev);
|
||||
|
||||
#endif
|
||||
|
||||
void rs780_enable(device_t dev);
|
||||
void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port);
|
||||
void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port);
|
||||
void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
|
||||
void config_gpp_core(device_t nb_dev, device_t sb_dev);
|
||||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
|
||||
u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
|
||||
u32 extractbit(u32 data, int bit_number);
|
||||
u32 extractbits(u32 source, int lsb, int msb);
|
||||
int cpuidFamily(void);
|
||||
int is_family0Fh(void);
|
||||
int is_family10h(void);
|
||||
void pcie_hide_unused_ports(device_t nb_dev);
|
||||
|
||||
void enable_rs780_dev8(void);
|
||||
void rs780_early_setup(void);
|
||||
void rs780_htinit(void);
|
||||
|
||||
#endif /* __RS780_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue