Bellongs to r3946
Following patch adds dynamically generated P-States infrastructure as well as M2V-MX SE as example how to do that. It is based on AMD code and mine code for ACPI generation. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Rudolf Marek
parent
f997b5554a
commit
537bd5f637
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@ -0,0 +1,386 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License v2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <arch/acpigen.h>
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#include <cpu/amd/model_fxx_powernow.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/amdk8_sysconf.h>
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#include <arch/cpu.h>
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static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
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u8 *pstate_fid, u32 *pstate_power, int coreID,
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u32 pcontrol_blk, u8 plen, u8 onlyBSP) {
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int lenp, lenpr, i;
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if ((onlyBSP) && (coreID != 0)) {
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plen = 0;
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pcontrol_blk = 0;
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}
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lenpr = acpigen_write_processor(coreID, pcontrol_blk, plen);
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lenpr += acpigen_write_empty_PCT();
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lenpr += acpigen_write_name("_PSS");
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/* add later to total sum */
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lenp = acpigen_write_package(pstate_num);
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for (i = 0;i < pstate_num;i++) {
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u32 control, status;
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control =
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(0x3 << 30) | /* IRT */
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(0x2 << 28) | /* RVO */
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(0x1 << 27) | /* ExtType */
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(0x2 << 20) | /* PLL_LOCK_TIME */
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(0x0 << 18) | /* MVS */
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(0x5 << 11) | /* VST */
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(pstate_vid[i] << 6) |
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pstate_fid[i];
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status =
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(pstate_vid[i] << 6) |
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pstate_fid[i];
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lenp += acpigen_write_PSS_package(pstate_feq[i],
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pstate_power[i],
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0x64,
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0x7,
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control,
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status);
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}
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/* update the package size */
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acpigen_patch_len(lenp - 1);
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lenpr += lenp;
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lenpr += acpigen_write_PPC(pstate_num);
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/* patch the whole Processor token length */
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acpigen_patch_len(lenpr - 2);
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return lenpr;
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}
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/*
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* Details about this algorithm , refert to BDKG 10.5.1
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* Two parts are included, the another is the DSDT reconstruction process
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*/
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static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
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{
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int len;
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u8 processor_brand[49];
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u32 *v;
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struct cpuid_result cpuid1;
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struct power_limit_encoding {
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u8 socket_type;
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u8 cmp_cap;
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u8 pwr_lmt;
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u32 power_limit;
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};
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u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
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u16 Max_feq;
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u8 Pstate_fid[10];
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u16 Pstate_feq[10];
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u8 Pstate_vid[10];
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u32 Pstate_power[10];
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u32 Pstate_volt[10];
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u8 PstateStep, PstateStep_coef;
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u8 IntPstateSup;
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u8 Pstate_num;
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u16 Cur_feq;
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u8 Cur_fid;
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u8 cmp_cap, pwr_lmt;
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u32 power_limit = 0;
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u8 index;
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msr_t msr;
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u32 fid_multiplier;
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static struct power_limit_encoding TDP[20] = {
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{0x11, 0x0, 0x8, 62},
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{0x11, 0x1, 0x8, 89},
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{0x11, 0x1, 0xa, 103},
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{0x11, 0x1, 0xc, 125},
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{0x11, 0x0, 0x2, 15},
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{0x11, 0x0, 0x4, 35},
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{0x11, 0x1, 0x2, 35},
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{0x11, 0x0, 0x5, 45},
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{0x11, 0x1, 0x7, 76},
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{0x11, 0x1, 0x6, 65},
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{0x11, 0x1, 0x8, 89},
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{0x11, 0x0, 0x1, 8},
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{0x11, 0x1, 0x1, 22},
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{0x12, 0x0, 0x6, 25},
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{0x12, 0x0, 0x1, 8},
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{0x12, 0x0, 0x2, 9},
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{0x12, 0x0, 0x4, 15},
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{0x12, 0x0, 0xc, 35},
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{0x12, 0x1, 0xc, 35},
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{0x12, 0x1, 0x4, 20}
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};
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/* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
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cpuid1 = cpuid(0x80000002);
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v = (u32 *) processor_brand;
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v[0] = cpuid1.eax;
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v[1] = cpuid1.ebx;
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v[2] = cpuid1.ecx;
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v[3] = cpuid1.edx;
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cpuid1 = cpuid(0x80000003);
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v[4] = cpuid1.eax;
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v[5] = cpuid1.ebx;
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v[6] = cpuid1.ecx;
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v[7] = cpuid1.edx;
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cpuid1 = cpuid(0x80000004);
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v[8] = cpuid1.eax;
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v[9] = cpuid1.ebx;
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v[10] = cpuid1.ecx;
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v[11] = cpuid1.edx;
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processor_brand[48] = 0;
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printk_info("processor_brand=%s\n", processor_brand);
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/*
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* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
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* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
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* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
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*/
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printk_info("Pstates Algorithm ...\n");
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cmp_cap =
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(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
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0x3000) >> 12;
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cpuid1 = cpuid(0x80000001);
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pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
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for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
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if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
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TDP[index].cmp_cap == cmp_cap &&
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TDP[index].pwr_lmt == pwr_lmt) {
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power_limit = TDP[index].power_limit;
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}
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Pstate_num = 0;
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/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
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cpuid1 = cpuid(0x80000007);
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if ((cpuid1.edx & 0x6) != 0x6) {
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printk_info("No valid set of P-states\n");
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goto write_pstates;
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}
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msr = rdmsr(0xc0010042);
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Max_fid = (msr.lo & 0x3F0000) >> 16;
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Start_fid = (msr.lo & 0x3F00) >> 8;
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Max_vid = (msr.hi & 0x3F0000) >> 16;
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Start_vid = (msr.hi & 0x3F00) >> 8;
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PstateStep = (msr.hi & 0x1000000) >> 24;
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IntPstateSup = (msr.hi & 0x20000000) >> 29;
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/*
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* The P1...P[Min+1] VID need PstateStep to calculate
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* P[N] = P[N-1]VID + 2^PstateStep
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* PstateStep_coef = 2^PstateStep
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*/
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if (PstateStep == 0)
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PstateStep_coef = 1;
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else
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PstateStep_coef = 2;
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if (IntPstateSup == 0) {
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printk_info("No intermediate P-states are supported\n");
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goto write_pstates;
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}
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/* Get the multipier of the fid frequency */
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/*
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* Fid multiplier is always 100 revF and revG.
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*/
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fid_multiplier = 100;
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/*
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* Formula1: CPUFreq = FID * fid_multiplier + 800
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* Formula2: CPUVolt = 1550 - VID * 25 (mv)
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* Formula3: Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
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*/
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/* Construct P0(P[Max]) state */
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Max_feq = Max_fid * fid_multiplier + 800;
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if (Max_fid == 0x2A && Max_vid != 0x0) {
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Min_fid = 0x2;
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Pstate_fid[0] = Start_fid + 0xA; /* Start Frequency + 1GHz */
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Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
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Min_vid = Start_vid;
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Pstate_vid[0] = Max_vid + 0x2; /* Maximum Voltage - 50mV */
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Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
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Pstate_power[0] = power_limit * 1000; /* mw */
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Pstate_num++;
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} else {
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Min_fid = Start_fid;
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Pstate_fid[0] = Max_fid;
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Pstate_feq[0] = Max_feq;
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Min_vid = Start_vid;
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Pstate_vid[0] = Max_vid + 0x2;
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Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
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Pstate_power[0] = power_limit * 1000; /* mw */
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Pstate_num++;
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}
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Cur_feq = Max_feq;
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Cur_fid = Max_fid;
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/* Construct P1 state */
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if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) { /* odd value */
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Pstate_fid[1] = Max_fid - 0x1;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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Pstate_num++;
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}
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if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) { /* even value */
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Pstate_fid[1] = Max_fid - 0x2;
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Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
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Cur_fid = Pstate_fid[1];
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Cur_feq = Pstate_feq[1];
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if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* odd value */
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Pstate_vid[1] = Pstate_vid[0] + 0x1;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) { /* even value */
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Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
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Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
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Pstate_power[1] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
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(Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
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}
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Pstate_num++;
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}
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/* Construct P2...P[Min-1] state */
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Cur_fid = Cur_fid - 0x2;
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Cur_feq = Cur_fid * fid_multiplier + 800;
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while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
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Pstate_fid[Pstate_num] = Cur_fid;
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Pstate_feq[Pstate_num] =
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Pstate_fid[Pstate_num] * fid_multiplier + 800;
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Cur_fid = Cur_fid - 0x2;
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Cur_feq = Cur_fid * fid_multiplier + 800;
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if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
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Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
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Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
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Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
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} else {
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Pstate_vid[Pstate_num] =
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Pstate_vid[Pstate_num - 1] + PstateStep_coef;
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Pstate_volt[Pstate_num] =
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1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num] / (Pstate_feq[0] *
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Pstate_volt[0] *
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Pstate_volt[0]);
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}
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Pstate_num++;
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}
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/* Constuct P[Min] State */
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if (Max_fid == 0x2A && Max_vid != 0x0) {
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Pstate_fid[Pstate_num] = 0x2;
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Pstate_feq[Pstate_num] =
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Pstate_fid[Pstate_num] * fid_multiplier + 800;
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Pstate_vid[Pstate_num] = Min_vid;
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Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
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Pstate_volt[0]);
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Pstate_num++;
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} else {
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Pstate_fid[Pstate_num] = Start_fid;
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Pstate_feq[Pstate_num] =
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Pstate_fid[Pstate_num] * fid_multiplier + 800;
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Pstate_vid[Pstate_num] = Min_vid;
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Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
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Pstate_power[Pstate_num] =
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(unsigned long long)Pstate_power[0] *
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Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
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Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
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Pstate_volt[0]);
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Pstate_num++;
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}
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/* Print Pstate freq,vid,volt,power */
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for (index = 0; index < Pstate_num; index++) {
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printk_info("Pstate_freq[%d] = %dMHz\t", index,
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Pstate_feq[index]);
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printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
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printk_info("Pstate_volt[%d] = %dmv\t", index,
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Pstate_volt[index]);
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printk_info("Pstate_power[%d] = %dmw\n", index,
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Pstate_power[index]);
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}
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write_pstates:
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len = 0;
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for (index = 0; index < (cmp_cap + 1); index++) {
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len += write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid,
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Pstate_fid, Pstate_power, index,
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pcontrol_blk, plen, onlyBSP);
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}
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return len;
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}
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int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) {
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int lens;
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char pscope[] = "\\_PR_";
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lens = acpigen_write_scope(pscope);
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lens += pstates_algorithm(pcontrol_blk, plen, onlyBSP);
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//minus opcode
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acpigen_patch_len(lens - 1);
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return lens;
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}
|
||||
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Reference in New Issue