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mb/intel/tglrvp : Enable RP LTR 

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I8ab7667d788563ffcb9287a64254590ef9bea5d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40269
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-04-07 23:37:11 -07:00 committed by Patrick Georgi
parent e3bf8ba2d8
commit 53ac68e551
2 changed files with 12 additions and 0 deletions
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6
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1" register "PcieRpEnable[10]" = "1"
# Enable RP LTR
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Hybrid storage mode # Hybrid storage mode
register "HybridStorageMode" = "1" register "HybridStorageMode" = "1"

6
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -45,6 +45,12 @@ chip soc/intel/tigerlake
register "PcieRpEnable[8]" = "1" register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[10]" = "1" register "PcieRpEnable[10]" = "1"
# Enable PR LTR
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Hybrid storage mode # Hybrid storage mode
register "HybridStorageMode" = "1" register "HybridStorageMode" = "1"