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mb/google/volteer: Enable RP LTR setting 

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ibbf55e6a08ff5e8f358325bb8e9f1487cc982f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40268
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-04-07 23:34:12 -07:00 committed by Patrick Georgi
parent 5943117647
commit e3bf8ba2d8
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -43,20 +43,24 @@ chip soc/intel/tigerlake
# Enable NVMe PCIE 9 using clk 0
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
# Enable Optane PCIE 11 using clk 0
register "PcieRpEnable[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
register "HybridStorageMode" = "1"
# Enable SD Card PCIE 8 using clk 3
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
# Enable WLAN PCIE 7 using clk 1
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"